JPS57133651A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS57133651A
JPS57133651A JP56019228A JP1922881A JPS57133651A JP S57133651 A JPS57133651 A JP S57133651A JP 56019228 A JP56019228 A JP 56019228A JP 1922881 A JP1922881 A JP 1922881A JP S57133651 A JPS57133651 A JP S57133651A
Authority
JP
Japan
Prior art keywords
pad
outgoing
testing
chip
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56019228A
Other languages
Japanese (ja)
Inventor
Michihiro Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56019228A priority Critical patent/JPS57133651A/en
Publication of JPS57133651A publication Critical patent/JPS57133651A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To assure external connection, improve yield in manufacture and to enhance the reliability by a method wherein two or more outgoing electrode pads are provided for an IC chip are formed per optional electrode terminal to be used for characteristics evaluation, connection and the like as necessary. CONSTITUTION:For the sample, an internal Al wiring and an electrode pad are formed into a shape wherein electrode pads 2 and 22 for an optional outgoing terminal are connected to each other on an IC chip whereon oxidation, diffusion and the like treatment are performed. Then after the probe testing the chip performance using the pad 2, a thick film metal bump 3 is formd by Ti, Cr, solder or the like into the pad 22 to connect to say the outgoing lead 4 of the film carrier. Otherwise, after the testing, the pad 22 connected to a wire is assembled into package. Through these procedures, the terminals may be firmly connected with excellent adhesive property, when they are assembled by a method wherein the connecting pad 22 will not be damaged when a characteristics testing is performed.
JP56019228A 1981-02-12 1981-02-12 Semiconductor integrated circuit device Pending JPS57133651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56019228A JPS57133651A (en) 1981-02-12 1981-02-12 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56019228A JPS57133651A (en) 1981-02-12 1981-02-12 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS57133651A true JPS57133651A (en) 1982-08-18

Family

ID=11993512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56019228A Pending JPS57133651A (en) 1981-02-12 1981-02-12 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57133651A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59127852A (en) * 1983-01-12 1984-07-23 Matsushita Electronics Corp Semiconductor device
JPS59186347A (en) * 1983-04-06 1984-10-23 Nec Corp Terminal structure of integrated circuit
US5168342A (en) * 1989-01-30 1992-12-01 Hitachi, Ltd. Semiconductor integrated circuit device and manufacturing method of the same
US5442241A (en) * 1993-07-26 1995-08-15 Kabushiki Kaisha Toshiba Bump electrode structure to be coupled to lead wire in semiconductor device
US5554940A (en) * 1994-07-05 1996-09-10 Motorola, Inc. Bumped semiconductor device and method for probing the same
JP2002190494A (en) * 2000-12-22 2002-07-05 Shinkawa Ltd Apparatus for bonding data setting and method therefor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59127852A (en) * 1983-01-12 1984-07-23 Matsushita Electronics Corp Semiconductor device
JPS59186347A (en) * 1983-04-06 1984-10-23 Nec Corp Terminal structure of integrated circuit
US5168342A (en) * 1989-01-30 1992-12-01 Hitachi, Ltd. Semiconductor integrated circuit device and manufacturing method of the same
US5442241A (en) * 1993-07-26 1995-08-15 Kabushiki Kaisha Toshiba Bump electrode structure to be coupled to lead wire in semiconductor device
US5554940A (en) * 1994-07-05 1996-09-10 Motorola, Inc. Bumped semiconductor device and method for probing the same
JP2002190494A (en) * 2000-12-22 2002-07-05 Shinkawa Ltd Apparatus for bonding data setting and method therefor

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