JPS57132327A - Measurement of superposition accuracy of mask for integrated circuit - Google Patents

Measurement of superposition accuracy of mask for integrated circuit

Info

Publication number
JPS57132327A
JPS57132327A JP1693781A JP1693781A JPS57132327A JP S57132327 A JPS57132327 A JP S57132327A JP 1693781 A JP1693781 A JP 1693781A JP 1693781 A JP1693781 A JP 1693781A JP S57132327 A JPS57132327 A JP S57132327A
Authority
JP
Japan
Prior art keywords
test pattern
deltal
mask
integrated circuit
superposition accuracy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1693781A
Other languages
Japanese (ja)
Inventor
Yasuro Tosaka
Yoshio Tanaka
Kosuke Uchiho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP1693781A priority Critical patent/JPS57132327A/en
Publication of JPS57132327A publication Critical patent/JPS57132327A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To simply obtain the superposition accuracy of a mask for integrated circuit by a method wherein a plurality of test pattern layers are superimposed on a substrate for exposure and the dimension between each printed test pattern is measured. CONSTITUTION:The distance (a) between the first-layer test pattern 311, and the second-layer test pattern 32 and that (b) between the second-layer test pattern 32 and the first-layer test pattern 312 are measured by a microdimension measuring device. If these test patterns 311, 312, 32 are printed in accordance with design, a=b is established because the test pattern 32 is designed to be exactly located at the middle of the test patterns 311 and 312. On the other hand, if the test pattern 32 is printed by deviating by DELTAl, a=l+DELTAl, b=l-DELTAl are established to form anot equal to b. The DELTAl can be obtained by calculating (a-b)/2. If this way, superposition accuracy can simply be obtained by measuring the dimension between each test pattern.
JP1693781A 1981-02-09 1981-02-09 Measurement of superposition accuracy of mask for integrated circuit Pending JPS57132327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1693781A JPS57132327A (en) 1981-02-09 1981-02-09 Measurement of superposition accuracy of mask for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1693781A JPS57132327A (en) 1981-02-09 1981-02-09 Measurement of superposition accuracy of mask for integrated circuit

Publications (1)

Publication Number Publication Date
JPS57132327A true JPS57132327A (en) 1982-08-16

Family

ID=11930031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1693781A Pending JPS57132327A (en) 1981-02-09 1981-02-09 Measurement of superposition accuracy of mask for integrated circuit

Country Status (1)

Country Link
JP (1) JPS57132327A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5691424A (en) * 1979-12-25 1981-07-24 Seiko Epson Corp Mask accuracy measuring pattern
JPS5769742A (en) * 1980-10-20 1982-04-28 Sanyo Electric Co Ltd Inspecting method for accuracy of pattern

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5691424A (en) * 1979-12-25 1981-07-24 Seiko Epson Corp Mask accuracy measuring pattern
JPS5769742A (en) * 1980-10-20 1982-04-28 Sanyo Electric Co Ltd Inspecting method for accuracy of pattern

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