JPS57125441A - Operaton system - Google Patents
Operaton systemInfo
- Publication number
- JPS57125441A JPS57125441A JP56011173A JP1117381A JPS57125441A JP S57125441 A JPS57125441 A JP S57125441A JP 56011173 A JP56011173 A JP 56011173A JP 1117381 A JP1117381 A JP 1117381A JP S57125441 A JPS57125441 A JP S57125441A
- Authority
- JP
- Japan
- Prior art keywords
- register
- latch
- private
- unit
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To make the operation processing high-speed, by reducing the number of decision branches of a microprogram for the byte processing of decimal operation instructions to take out the result easily by providing a private register, a loop counter and a control latch. CONSTITUTION:A private binary adder 63 private registers 61 and 62, and private control latches 64-66 are provided for anarithmetic unit 20 of a computer system. The 6th byte of a bus 232 of the unit 20 is set to the register 61, and one digit of the register 61 or the output of the adder 63 is set to the register 62, and ''1'' is added to the value of the register 62 or is subtracted from it by the adder 63, and the result is returned to the register 61. The latch 64 indicates whether subtraction is executed in the loop or not, and the latch 65 indicates whether subtaction is executed in the preceding loop, and the latch 66 indicates suppression of setting of a work register. The value of the register 61 is set to latches 64-66, and the operation control of the unit 20 is used to reduce the number of branches of the program.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56011173A JPS57125441A (en) | 1981-01-27 | 1981-01-27 | Operaton system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56011173A JPS57125441A (en) | 1981-01-27 | 1981-01-27 | Operaton system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57125441A true JPS57125441A (en) | 1982-08-04 |
JPS6143735B2 JPS6143735B2 (en) | 1986-09-29 |
Family
ID=11770659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56011173A Granted JPS57125441A (en) | 1981-01-27 | 1981-01-27 | Operaton system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57125441A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01293437A (en) * | 1988-05-20 | 1989-11-27 | Hitachi Ltd | Decimal multiplier |
-
1981
- 1981-01-27 JP JP56011173A patent/JPS57125441A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01293437A (en) * | 1988-05-20 | 1989-11-27 | Hitachi Ltd | Decimal multiplier |
Also Published As
Publication number | Publication date |
---|---|
JPS6143735B2 (en) | 1986-09-29 |
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