JPS57121736A - Multiinput adder - Google Patents

Multiinput adder

Info

Publication number
JPS57121736A
JPS57121736A JP56006465A JP646581A JPS57121736A JP S57121736 A JPS57121736 A JP S57121736A JP 56006465 A JP56006465 A JP 56006465A JP 646581 A JP646581 A JP 646581A JP S57121736 A JPS57121736 A JP S57121736A
Authority
JP
Japan
Prior art keywords
code bit
output terminal
digit
code
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56006465A
Other languages
Japanese (ja)
Other versions
JPH0127452B2 (en
Inventor
Tadanobu Nikaido
Takatoshi Nakajima
Hiroki Yamauchi
Fumihiko Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56006465A priority Critical patent/JPS57121736A/en
Publication of JPS57121736A publication Critical patent/JPS57121736A/en
Publication of JPH0127452B2 publication Critical patent/JPH0127452B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To decrease the quantity of hardware required for adding a code extension term, by adding inverted information of each code bit, and a fixed data ''1'' instead of adding a code bit as it is as the code extension term. CONSTITUTION:All adders 2-7, 10, 11 and 14 add information inputted to input terminals 1, 2 and 3, and output the sum and the carry to an output terminal 4 and an output terminal 5, respectively. Also, half-adders 1, 8, 9, 12 and 13 add information inputted to input terminals 1, 2, and output the sum and the carry to the output terminal 4 and the output terminal 5, respectively. Subsequently, in each digit extending from the lowest digit of each code bit to the highest digit, in 4 binary numbers, ''1'' is supplied to 2<3>, 2<4> and 2<7> being digits except those which have a code bit, that is to say, 2<2>, 2<5>, 2<6> and 2<8>, and also to the lowest digit among the digits having a code bit, that is to say, 2<2>, as addition data.
JP56006465A 1981-01-21 1981-01-21 Multiinput adder Granted JPS57121736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56006465A JPS57121736A (en) 1981-01-21 1981-01-21 Multiinput adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56006465A JPS57121736A (en) 1981-01-21 1981-01-21 Multiinput adder

Publications (2)

Publication Number Publication Date
JPS57121736A true JPS57121736A (en) 1982-07-29
JPH0127452B2 JPH0127452B2 (en) 1989-05-29

Family

ID=11639190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56006465A Granted JPS57121736A (en) 1981-01-21 1981-01-21 Multiinput adder

Country Status (1)

Country Link
JP (1) JPS57121736A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920498A (en) * 1996-08-29 1999-07-06 Fujitsu Limited Compression circuit of an adder circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920498A (en) * 1996-08-29 1999-07-06 Fujitsu Limited Compression circuit of an adder circuit
US6240438B1 (en) 1996-08-29 2001-05-29 Fujitsu Limited Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability
US6535902B2 (en) 1996-08-29 2003-03-18 Fujitsu Limited Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability

Also Published As

Publication number Publication date
JPH0127452B2 (en) 1989-05-29

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