SU1481897A1 - Converter of binary numbers to binary-coded decimal numbers - Google Patents

Abstract

The invention relates to computing. The aim of the invention is to increase speed. To do this, in the converter of binary numbers to binary-decimal, containing bit converters 1-4 and binary-decimal adders 11-13, the latter are connected in a pyramid scheme and made of binary adders 5, 6, 9 and adders 7, 8, 10 correction. In this case, the inverse transfer outputs of odd binary adders are connected to the subtraction inputs (-6) of the corresponding correction adders, and the direct transfer outputs of even binary adders are connected to the addition inputs (+6) of the corresponding correction adders. 1 il.

Description

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The invention relates to automation and digital computing and can be used in the construction of a binary-decimal converter.

The aim of the invention is to increase speed.

The drawing shows a block diagram of the Converter.

The converter circuit contains bit converters 1-4, binary adders 5 and 6, adders 7 and 8 corrections, a binary adder 9, adder 10 corrections. Binary adders 5 and 6 and adders 7 and 8 of the correction together form the binary-decimal adders 11 and 12, which represent the first step of the summation. The binary adder 9 and the correction adder 10 together form a binary-decimal adder 13, representing the second step of the summation. Bit converters 1 to 4 can be performed on programmable storage devices (ROM).

The proposed Converter works as follows.

When the input binary code arrives at the converter inputs, the outputs of the ROM blocks 4, 2 and 1, 3 show, respectively, binary-decimal codes and binary-decimal codes with an excess of six, equivalent to the terms of the original binary number.

Binary-decimal addition is carried out in a code with an excess of six and subsequent correction of the result. This code is obtained by adding to the content of each tetrad a binary-decimal number six. The correction of the result consists in subtracting the number six from the contents of those tetrad, where there was no intertext transfer.

In each of the blocks of ROM 2 and 4, natural binary-decimal codes for all binary numbers of this group are entered. In each of the ROM 1 and 3 blocks, binary-decimal codes are entered with an excess of six for all binary numbers of this group. The mixed result code obtained at the output of binary adder 5 is corrected in the natural binary-decimal code by the adder 7 of the first stage.

For this, each tetrad of the adder 7 is summed with the code 0000, if

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there is an intertext transfer from this tetrad p of adder 5, and with code 1010, if there is no intertext transfer from this tetrad of adder 5, the subtraction operation of the excess six is replaced by addition with its addition (1010). The mixed result code obtained at the output of the adder 6 is corrected to a binary-decimal code with an excess of six by the adder 8 of the correction. For this, each tetrad of the adder 8 of the correction is summed with the binary code 0000 if there is no inter-tetrant transfer from this tetrad of the adder 6, and with the IT code if there is an inter-tetrant transfer from this tetrad of the adder 6.

The natural binary-decimal code from the outputs of the correction adder 7 and the binary-decimal code with an excess of six from the outputs of the adder 8 correction arrive at the inputs of the first and second components of the adder 9 of the second stage. The code obtained at the outputs of the adder 9 is corrected to the natural binary-decimal code by the adder 10 of the correction. For this, each tetrad of the correction adder 10 is summed with a code 0000 if there is an intertext transfer from a given tetrad of the adder 9, and with a binary code 1010 if the indicated transfer is absent.

Depending on the value of the higher bit of the input number received at the first inputs of the ROM blocks 1-4, a memory area is selected that corresponds to a positive or negative input number. The contents for memory cells for both positive and negative binary numbers are positive decimal equivalents, since decimal numbers must be represented in a direct code.

The sign of the input number can be transmitted to the converter output as the fourth digit of the sign tetrad, the first and third digit of the sign tetrad and the second digit of the sign tetrad are connected (for KOI-8 code), respectively, to the inputs of logical G1 and O, converter.

Examples of binary to decimal converters. Example 1

Example 2

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Claims (1)

Invention Formula The converter of binary numbers to binary-decimal, containing the stages of binary-decimal adders and a group of bit converters, the inputs of the lower bits of which are connected to the inputs of the corresponding bits of the converter, the sign input of which is connected to the inputs of the old and amp digit of all bit converters and is the output of the sign of the converter, whose information outputs are the outputs of the last binary-decimal adder, the outputs of the first and second bit converters are connected respectively first and second inputs of the first binary-decimal adder of the first stage, the outputs of the first binary-decimal adder of each stage are connected to the first inputs of the first adder of the next higher stage, characterized in that, in order to increase speed, the outputs of the 1st ( 1 1- n / tn) an odd-bit converter is connected to the first inputs (binary-decimal adder of the first stage, and the outputs of the 1st even-digit converter are connected to 897b  i the second inputs of the -th binary-decimal adder of the first stage, where n, m are the widths of the input code and the bit converter, respectively, the outputs of the odd binary-decimal adders of each stage are connected to the first inputs of the binary primary adders of the next highest stage, the second inputs which are connected to the outputs of the even binary decimal adders of the next lower stage, all of the binary decimal adders contain a correction adder divided into tetrads and a binary adder, and the wasp of each tetrad of odd binary adders of each stage is connected to the inputs of the second and fourth bits of the corresponding tetrad of correction adders, the inputs of the first and third bits of which are connected to the input of the logical zero of the converter, the second transfer of each tetrad of even binary binary adders are connected to the input of the second and the third bits of the corresponding correction adders, the inputs of the first 0 and the fourth bits of which are connected to the input of the logical zero of the converter.