JPS57121318A - Decode circuit - Google Patents

Abstract

PURPOSE:To access a memory cell in a high speed in (a) continuous access mode, by connecting column decoders of an RAM through a shift register to constitute a closed circuit. CONSTITUTION:In case that a decode circuit having the shift register function is applied to the selecting circuit for I/O bus pairs of a memory circuit which can be accessed in a continuous access mode and has plural I/O bus pairs, decode information is taken into a latch circuit by the first clock phiL, and decode information is transferred to the decoder of the next stage by the second clock phiT. In respect to transistors TRs QA and QB which generate transfer information, the former resets the output node point of the decode circuit to the earth potential after the start of transfer, and the latter charges selectively the output constact of the decode circuit of the next stage. A TR QD is provided which resets the raised potential at a node point RO to the earth potential by the clock phiL after information transfer due to the clock phiT.