JPS6058555B2 - decoding circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a decoding circuit.

In a multi-address type MOS semiconductor memory having a row address latch means and a column address latch means, a decoder that determines a row address and a column address, respectively, is originally intended for random access. Separate and independent circuit configurations are taken for each address, and row and column addresses are set for each cycle.
So-called 'page mode', which features high-speed access
'It was necessary to supply a column address each time the cycle occurred.

This RAS (Row Address Strobe) clock and CAS (Column
Due to recent dramatic advances in semiconductor technology, the capacity of MOS random access memory (RAM), which uses a two-phase clock using a nAddress Strobe (column address strobe) clock and a multi-address system, continues to increase. Currently, 64-bit memory has been put into practical use.

Such high-density memory is often used as the main memory (hereinafter referred to as main memory) of large and ultra-large computers, but in these systems the central processing unit (hereinafter referred to as C
In order to increase the overall processing power of the CPU (hereinafter referred to as PU), a buffer storage device (hereinafter referred to as buffer memory) exists between the CPU and main memory. This buffer memory is CPU
Its main function is to temporarily store information that is mutually exchanged between the main memory and the main memory, but in order to compensate for the difference in operating speed, consecutive addresses are allocated to multiple storage modules in the main memory to achieve high-speed processing. The interleaf method is used to access these one after another, and the information exchanged is a series of fixed-length consecutive addresses, and the multi-address RAM is characterized by its unique high-speed access. ``Page mode'' cycles are also rarely used, making high-density, large-capacity memories with large word counts and 1-bit configurations unsuitable for these applications. From the above background,
In a multi-address RAM using two-phase RAS and CAS clocks, instead of 'page mode', in the normal RAS/CAS cycle, the internal memory is processed based on the supplied address information and only by the continuously supplied CAS clock. Patent Application No. 55-100850 discloses a memory circuit featuring continuous access mode, which generates column addresses in 100 kHz and eliminates the need to supply external addresses, allowing for faster operation than page mode. devised.

According to the invention, a shift register is incorporated into a column decoder capable of high-speed random operation of memory cells in the conventional page mode, and the shift operation by the shift register is effectively utilized to further increase the speed and supply external addresses. The present invention provides a memory circuit characterized in that memory cells allocated to consecutive column addresses can be accessed without having to do so. An object of the present invention is to use a multi-address system RAr! using two-phase clocks. The object of the present invention is to provide a decoding circuit that can access a series of arbitrary or specific length consecutive addresses in the column direction at higher speed.

The decoding circuit of the present invention employs a conventional multi-address system using a two-phase clock, with memory cells arranged in a matrix of M rows and N columns, a row decoder that selects M rows, and a column that selects N columns. In a RAM configured by a decoder, a shift register is especially built into the column decoder, and adjacent column decoders are connected one after another through this, and the Nth column decoder connects the first column through the Nth shift register. This is obtained by constructing a closed circuit connected to the decoder.

What is the decoding circuit obtained by this? No/G? During a cycle, first arbitrary row and address information are respectively taken in, memory cells are accessed, and column decoder selection/non-selection information based on column address information is taken into the shift register. After that, when moving to continuous access cycle, Q? By a clock generated in synchronization with the clock only? Starts the operation of transferring the column address information taken in the No/a No cycle. Holding and transfer of address information by the decoder with shift register are performed by a holding clock generated during the activation period of the a/no clock and a transfer lock occurring during the reset period of the 0/no clock, respectively.
done bit by bit. As a result, accesses to memory cells in this continuous access mode are taken in by the conventional column address buffer, and consecutive addresses can always be accessed without requiring column address information obtained. Also, d?
In the method of generating a transfer lock during the reset period of , it is already known that the next address will always be accessed in the next cycle, so the Q? Another benefit is that the transfer of column information to the adjacent decoder and the determination of the adjacent decoder during the reset period of the process are enabled, and the cycle of continuous access mode can also be significantly shortened. Moreover, normal? In the q/a fail cycle, only a holding clock is generated and the setting is such that a transfer lock does not occur, so the column address information is only captured in the register, and the function as a normal column decoder is not impaired in any way. . Furthermore, this retention function allows normal ? Since the column address information and the corresponding held information can be updated every No/G No cycle, the column atos information can be transferred smoothly in response to a transition to a continuous access cycle. This will be explained below using the drawings.

FIG. 1 shows a (M rows x N columns) word x 1 bit two-phase clock multi-address RAM in continuous access mode that incorporates a decoder with a shift register according to the present invention.
An example of the configuration is shown below.

The memory cells are arranged in a matrix 11 of M rows and N columns, and each row and column is selected by an X decoder 12, a Y decoder 1, and a Y decoder 15 with a shift register. The X and Y decoders are supplied with address data from X and Y address buffers (not shown), respectively. M
When one X-decoder 12 is selected, a word line connected to it is selected, and N memory cells connected to this word line are simultaneously accessed and their data is transmitted to N sense amplifiers.The address signal from the Y address buffer is supplied to the Y decoder 14 and the Y decoder with shift register 15, respectively.
The Y decoder 14 selects L bits of the memory cell data at the x address and switches the input/output switches 13 to transmit each bit to L pairs of I/0 buses. The other address signal is sent to another Y decoder 15 equipped with a shift register.
It has the function of selecting any one of the L pairs of I/O buses. Furthermore, when moving to a continuous access cycle, Q? Every time a clock is input, the shift registers are operated by the shift register group that is generated, and the shift register is operated by the shift register group that is generated. The next address among the L I/O bus pairs selected according to the Y address information taken in the q/d fail cycle is sequentially selected. In this method, access can be made from any address among the L bits, and any number of consecutive addresses within the selected L bits can be accessed. It goes without saying that accessing more than L bits is also possible if the condition of L≦N is satisfied and the necessary I/0 bus pair is prepared. FIG. 2 shows a Y with shift register SR in one embodiment of FIG.
The decoder 20 provides L pairs of input/output buses I/00 and I/0.
0 to I/0L, select I/0L and connect a pair of data buses D
A method of coupling to I/0 and DI/0 will be shown, and a simple register operation will be explained using this method.

Takumi? The X address signal is latched by the falling edge of the clock, the X address buffer operates, an address binary code is generated, and one decoder is selected from among M X decoders. After X decoder selection, one word line is selected, the memory cells connected to it are selected, and the memory cell information is subsequently transmitted to the sense amplifier and amplified. The Y address signal is latched by the falling edge of the clock, and the Y address buffer, Y
A series of operations with the address decoder continues, and of the M bits of memory cell information selected by the X decoder, L bits selected by the Y decoder are transmitted to the input/output bus I/O. Furthermore, part of the branched address information 21 from the Y address buffer is transmitted to the Y decoder 20 with shift register SR, and transfer gate transistors TFA and TFB are controlled by the Y decoder output YEO.
The signal is transmitted to data buses DI/0 and DI/O via. Normally, the selection of the decoder is determined in the memory circuit.
), unselected decoders are designed to have internal MOS low level (logic level "08"). Therefore, Y decoder 2
When determining 0, only one bit of the Y decoder with L-bit shift register is ゛゜1゛, and the remaining decoders are ゛゜1゛.
Is this state the first state? It is taken into the shift register SR and held in the q/a occupation cycle. The shift register SR takes in decoded information by the holding clock generated every cycle as long as the smart history/G failure cycle continues, and updates the information in the shift register each time. After that, when switching to continuous access mode, Q
The transfer lock and hold clocks synchronized with the g clock are generated, and the shift register SR is in the ? Based on the decoding information taken in in the history/d/no cycle, data transfer is thereafter started bit by bit. Since a closed loop is configured such that the output of the last bit of the shift register SR is fed back to the first bit, the information in the shift register is always ゜゜1゛ in any cycle, and the other bits are always ゜゜1゛. The state in which all remaining bits of the decoder are 0 is maintained, and there is no occurrence of decoder non-selection or multiple selection. As a result, the selection and necessary selection of the Y address decoder is determined only by the data held in the shift register SR, and furthermore, since the information amplified by the sense amplifier has already been transmitted to the L pairs of I/0 buses, , Since memory cell information can be transmitted to the output buffer using only the data bus buffer amplifier activation clock associated with the data bus supplied after selecting an I/0 bus pair, the access time in this mode is shorter than the access time in the conventional page mode. This can have a significant effect on reducing access time. Third
The figure shows the basic configuration of a decoding circuit having a shift register function according to the present invention.

FIG. 4 is based on the basic configuration of the present invention and shows the introduction of this into an I/O bus pair selection circuit of a memory circuit having multiple I/0 bus pairs capable of continuous access mode. After the decoded information is taken into the latch circuit by the clock φ, when the decoded information is transferred to the next-stage decoder by the second clock φT, a transmission signal is generated based on the decoded information accumulated at the latch circuit output node. By separating and making two transistors independent, two systems of signals are formed, one for immediately resetting the output node of the selected decoding circuit to the ground potential after the start of transfer, and the other for selectively charging the output node of the next-stage decoding circuit. The former is a transistor Q that immediately returns the increased potential of the node RO to the ground potential by the clock φ after the decode information is transferred by the clock φ. This shows a circuit with improved operating margin for shortening cycles in continuous access mode.
Normally, the operating amplitude of the clock that performs major functions such as latch and transfer is set to the power supply level, but the transfer operation of the clock φτ according to the present invention is performed during the reset period of 0 or no during continuous access cycles. If the ON/OFF reset period becomes extremely short, the selective charging will become insufficient and the potential of the output node of the next stage decoder will not be able to rise sufficiently, leading to the possibility that a decoder no selection state will occur. .

Therefore, in order to improve this drawback, the well-known bootstrap effect is used to quickly raise the potential of the information transmission signal using this acceleration effect, thereby securing a sufficient potential in a short period of time. , an example of a circuit with further improved operating margin is shown in FIG. FIG. 5 shows an embodiment of the present invention, and FIG. 6 shows timing waveforms during its operation.
Using this, its operation will be explained in detail.

Although 8 bits will be used to explain the operation, there is no limit to the number of bits in implementing the present invention, and it is clear that increasing or decreasing the number of bits will not impair the basic operation of the present invention. Generally, a RAM decoder has a NOR logic configuration. Fifth
In the figure, the decoder is composed of three 0R-coupled transistors for address binary codes, indicated by Q1 to Q4, and a load transistor controlled by a clock PYO. The first brown/Q? When address information is taken in in a cycle, an address binary code is generated by the address buffer, and before being transmitted to the address decoder, the clock PYO transitions from the 1 level to the 0 level and precharges. Complete. The address decoder's decision is then made depending on the address binary code it accepts.

If decoder DO is selected, the decoder D. O)N
The OR output node NORO is maintained at the 6'r1 level, and the NOR output nodes NORl of other non-selected decoders D1 to D7
~NOR7 all transition to ゜“0゛ level. After this, the generated clock φ causes transistors Q5 and Q
6, the node YEO rises and transfer gate transistors Q7 and Q8 are controlled, thereby transferring the information on the selected I/0 buses I/00 and I/00 to the data bus D.
It is transmitted to I/0 and D1/0. The clock φ is a clock that controls a transfer gate transistor that transmits memory cell information amplified by a sense amplifier based on the output of another Y decoder onto L pairs of I/0 buses during a normal brown-fail/a-fail cycle. In synchronization with the clock φ. are set to start up at almost the same time so that they do not precede each other. Efforts are made so as not to impede the increase in access time during the history/Gq cycle. Also, is the clock φ q/O? It plays the role of latching Y address information during a cycle. That is, Figure ヰQ, ~Ql. The two-stage dynamic inverter connected with a ratio of .phi.5 and .phi.5 constitutes a latch circuit, and stores address decode information at node 8. The basic operation of this latch circuit is as follows. Takumi now? Decoder D in /σno cycle.

is selected. Therefore, the NOR of each decoder
The output nodes are each D. is at the logical ゜゜1゛ level, D1
~D, are all at the logic "゜0゛" level, and these become the input information of the shift register.When the clock φ is generated after each decoder makes a decision, the shift register SRO connected to the selected decoder D. starts the latch operation.Receiving the information ゜゜1゛ of the selection decoder DO, the transistor QlO turns ON, and the node 4 turns on the transistors Q9 and QlO.
In response to this, the transistor Ql2 turns 0FF, and the node 8 receives the clock φ. By turning ON the transistor Qll controlled by , the transistor Qll is charged to the VDO-■T (VT: threshold value of a MOS transistor) level. The level of the clock φ is set to raise the charging level of the node 8 as much as possible. It is set to D level. Is this latch circuit normal? Even if q/G no cycles continue, it is possible to latch update the decoder selection/non-selection information without any effect on the decoder. That is, decoder DO is selected in the first brown q/Q history cycle, and then the next ? Shift register S when another decoder is selected in no/0q cycle
The potential change at the decoder information storage node 8 in the RO is as follows. First, when the decoder DO is selected, the holding clock φ, which is generated thereafter, starts a latch operation in response to this, and sets the node 8 to V. Charge to O-V level.
next? ? /O? Decoder D in cycle. When becomes unselected, the node NORO goes to the '60'' level, turns off the transistor QlO, and charges the node A to the VDD-VT level by turning the clock φ. Immediately thereafter, the transistor Ql2 turns on, and the previous cycle The accumulated charges at node 8 are discharged.The accumulated charges at node 8 are discharged regardless of the holding clock φ in the next cycle, and the discharging transistor controlled by clock PYc is connected between node 8 and ground potential. Even if this is done every time the RAS/CAS cycle is reset, the basic operation of the shift register will not be impaired.At this time, other non-selected decoders such as shift register SRl connected to D1 , the transistor QlJ turns OFF and the transistor Ql2'' turns ON, so that the charge in the decoder information storage node 8'' remains discharged by the clock φ, and the ``0'' level is maintained. ? No/As long as the G history cycle continues, the decoder information is latched and updated in these shift registers, but after that, when the transition to a continuous access cycle using only the Qq clock occurs, ♂? Immediately after resetting, transfer lock φT occurs, and O? transfer operation during the reset period. Now, decoder D is in the brown q/d history cycle just before transitioning to the continuous access cycle.

is selected and the other decoder D. -DT becomes a non-selected state and then considers a case where the transition to a continuous access cycle occurs. At this time, the decoder information is latched by the clock φ during the Mjibe?g cycle, the node 8 in the shift register SRO goes to the 1 level, and the 8 in all other shift registers including the node 8 in the SRl The corresponding node is 6°05
゛ level. When the transfer lock φT, which is generated immediately after the reset of a and n, is entered, the node 8 is at the "L" level, so the transistor Ql7 turns 0N and starts charging the bootstrap capacitor CBO. Since the voltage is applied to the drain of Ql7, when the clock φe rises due to the bootstrap effect due to the drain-gate parasitic capacitance of the transistor Ql7 and the transistor Ql4 whose gate is connected to the node 8, the voltage at the node 8 changes from the VDD-VT level. Furthermore, the potential rises above the power supply level, accelerating the charging of the bootstrap capacitor CBO by the transistor Ql7.The charging level and time of the charging of the bootstrap capacitor CBO by the transistor Ql7 are determined by the ratio of the transistors Ql and Q2O and the transistor It is controlled by a delay circuit constituted by Q23 to Q26.After a certain appropriate delay time determined by the constant of the delay circuit, that is, the clock φT
Due to the rise in , node [F] rises, and in response to this, node 0 transitions from the ■DD-Vτ level to the 6"05' level, transistor Q2O is turned off, and the node [F] is connected to one end of the bootstrap capacitor CBO. 0 is opened to rise, and due to the well-known bootstrap effect, node PSYO starts to rise rapidly above the power supply level, turning transistor Q27 ON and node NORl, i.e., ?q/0, is selected during the negative cycle. The NOR output node NORl of the decoder D1 adjacent to the decoder D. In order to prevent the backflow of charges from node PSYO to clock φT, the potential of node 8 transitions from the "゜1゛" to the "゜"0゛ level, and the transistor Q17 is turned off.The transistor Q2l is turned off as the potential of node PSYO increases. C rises in parallel to the power supply level, and the potential change at node 8 is expressed as Q
In addition to 22 ON, increase. Transistor Ql8 discharges the accumulated charge in the bootstrap capacitor CBO by the holding clock φ generated during the activation period of the successive access cycle after transferring the decode information during the reset period of d/no, and lowers the potential of the node PSYO. On the other hand, in shift registers SRl to SR7 connected to non-selected decoders D1 to D7, all decoder information storage nodes, including node 8'' in shift register SRl, are maintained at the ``0'' level. Therefore, the transistors Ql4'' and Ql7'' are in the 0FF state, and the bootstrap capacitor is not charged due to the application of the transfer lock φT, and no rise in the potential of the node PSYl is observed.As described above, the transfer lock φτ is The selection or non-selection of the decoder during successive access cycles is made by selective charging of the decoder NOR output node by the transfer lock φ, which is an entirely new method never seen before. The transistor Ql4 increases the potential of the node [F] when the decoder information is transferred to the next-stage decoder by the clock φe, and in response to this, the transistor Ql5 is turned ON, and the selection information of the previous-stage decoder is 4'. It plays the role of transitioning the R3 level to the 640 step level and setting the selected decoder to a non-selected state.The transistor Ql6 prepares the potential of the node [F], which has reached the ゜“1゛ level, for the next cycle. During the activation period, the unselected decoder returns to the 660'' level. Also, in this continuous access cycle, the unselected decoder returns PSYi(1
= 0 to 7) is not performed, the NOR output node of each non-selected decoder becomes a floating potential of "゜0゛", which makes it susceptible to the effects of external noise etc., leading to the risk of multiple selection of decoders. When the decoder is not selected, the transistor Ql3 feeds back the output of the dynamic inverter consisting of Q9 and QlO, which operates in response to the "゜0゛ level" of the decoder NOR output node, and receives the logic ゜゜1゛ level of the node 8 whose potential has increased. , has a function of fixing the decoder NOR output node to ground potential. In this way, the flip-flop constituted by the transistor QlO and the transistor Ql3 based on the feedback of the output node of the inverter has the node 8 charged by the clock φ every cycle and maintained at the logic "1" level, so that it is not selected as a non-selected decoder. This function works to stably maintain the NOR output node at ground potential and prevent multiple selection from occurring. However, when the decoder transitions from required selection to selection, one of the flip-flops is used to ensure smooth operation. The dimension of transistor Ql3 is set to be as small as possible.Therefore, in consecutive access cycles when decoder DO is selected,
As PSY7 rises, NORO rises and transistor Ql. Since the node 8 is quickly returned to the ground potential by turning ON, the transfer operation using the clock φ can be performed smoothly. Also, what is the logic 66r3 level of node 4? In the history/G history cycle, the decoder precharge clock PYc. occurs, and all decoder output nodes NORi. (1=0 to 7) is charged to the logic ゛゜1゛ level, and the node 8 is also immediately returned to the ground potential, so that there is no problem in the holding operation of the shift register. The charging clock PYD of each decoder is set to the selected charging clock PSYi during the continuous access cycle. In order to rise above the current level and charge the selected decoder to the power supply level, it is set to be above the power supply level. or,
The address buffer that supplies the address binary code that is input to the decoder is set so that its operation is prohibited in continuous access mode. The above is a series of operations of the circuit according to the present invention. /Aq cycle a
Due to the holding clock φ which is generated synchronously, the decoder selection/non-selection information is taken into a latch circuit consisting of two extremely simple inverter stages, and it does not affect the next stage unless the transfer lock φτ is applied. Since the latch information can be updated without affecting the operation, the operation can be continued smoothly and quickly when transitioning to a continuous access cycle. Since the clock φ which also serves as the 0 bus information transfer drive signal can be latched in an extremely short time, the activation time can be shortened.Furthermore, the activation time can be shortened.
The transfer clock φT, which is generated immediately after the reset of , is accelerated due to the shortest bus from transistors Ql7 to Q27 in FIG. With a cycle time of 70NS, it is possible to achieve revolutionary performance not found in conventional dynamic memory circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a memory circuit incorporating a circuit according to the present invention. FIG. 2 is a diagram showing a driving method using a shift register. FIG. 3 shows a basic circuit of the present invention, and FIG. 4 shows a transmission information signal based on the present invention divided into two lines, one for resetting the selected decoder and the other for selecting and charging the next stage decoder.
FIG. 3 is a diagram showing a circuit with improved operating margin. FIG. 5 shows an embodiment of the present invention, and FIG. 6 is a timing waveform diagram based thereon. Codes in the diagram, QO~Q27, QA-QE
, Q3OO~QO2...MOS transistor, CBO
, CBl... capacitor.

Claims (1)

[Claims] 1 a load transistor controlled by an external signal;
In a decoding circuit having a plurality of driver transistors controlled by an address binary code, a latch circuit holds decoded output logic information under the control of a first signal, and a latch circuit holds decoded output logic information under the control of a first signal; a first transistor that gates a second signal under the control of decode information; a gate is connected to the output terminal of the first transistor and connected to a power supply and an output node of another decode circuit adjacent to the decode circuit; A decoding circuit comprising a second transistor connected thereto, and means for selectively charging the output of another adjacent decoding circuit based on decoding information.