JPS57117170A - Processing system for buffer memory coincidence - Google Patents

Processing system for buffer memory coincidence

Info

Publication number
JPS57117170A
JPS57117170A JP56001939A JP193981A JPS57117170A JP S57117170 A JPS57117170 A JP S57117170A JP 56001939 A JP56001939 A JP 56001939A JP 193981 A JP193981 A JP 193981A JP S57117170 A JPS57117170 A JP S57117170A
Authority
JP
Japan
Prior art keywords
memory
coincident
address
physical address
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56001939A
Other languages
Japanese (ja)
Other versions
JPS6138505B2 (en
Inventor
Masanobu Akagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56001939A priority Critical patent/JPS57117170A/en
Publication of JPS57117170A publication Critical patent/JPS57117170A/en
Publication of JPS6138505B2 publication Critical patent/JPS6138505B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To guarantee the proficiency of stored information of a tentative address buffer memory, by recognizing the stored location of corresponding information in a memory from a coincident processing physical address by using an inverting table and making coincident processing to all of the locations. CONSTITUTION:A stored address device 300 receives a coincident processing physical address from a memory controller 21 or a store control section 50 and gives it to a register 310 and a buffer memory 100. The content of the register 310 is given to an inversion table 400 as an address, and each set 401-404 gives one set of a physical address Q and a designated information S. Comparators 501-504 inform the presence of the location designated information S in memory 100 through the coincidence between the physical address of each set from the table 400 and that from the register 310 to a control section 601. Coincident processing control means 601 and 602 make coincident processing for all coincident sets to the block in the corresponding memory 100.
JP56001939A 1981-01-10 1981-01-10 Processing system for buffer memory coincidence Granted JPS57117170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56001939A JPS57117170A (en) 1981-01-10 1981-01-10 Processing system for buffer memory coincidence

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56001939A JPS57117170A (en) 1981-01-10 1981-01-10 Processing system for buffer memory coincidence

Publications (2)

Publication Number Publication Date
JPS57117170A true JPS57117170A (en) 1982-07-21
JPS6138505B2 JPS6138505B2 (en) 1986-08-29

Family

ID=11515573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56001939A Granted JPS57117170A (en) 1981-01-10 1981-01-10 Processing system for buffer memory coincidence

Country Status (1)

Country Link
JP (1) JPS57117170A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6451544A (en) * 1987-08-22 1989-02-27 Nec Corp Hierarchical cache device
JPH0221342A (en) * 1987-02-27 1990-01-24 Hitachi Ltd Logical cache memory
JPH03142644A (en) * 1989-10-30 1991-06-18 Hitachi Ltd Cache memory control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0221342A (en) * 1987-02-27 1990-01-24 Hitachi Ltd Logical cache memory
JPH0551937B2 (en) * 1987-02-27 1993-08-04 Hitachi Ltd
JPS6451544A (en) * 1987-08-22 1989-02-27 Nec Corp Hierarchical cache device
JPH03142644A (en) * 1989-10-30 1991-06-18 Hitachi Ltd Cache memory control system

Also Published As

Publication number Publication date
JPS6138505B2 (en) 1986-08-29

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