JPS54107636A - Address selection method for memory unit - Google Patents

Address selection method for memory unit

Info

Publication number
JPS54107636A
JPS54107636A JP1478278A JP1478278A JPS54107636A JP S54107636 A JPS54107636 A JP S54107636A JP 1478278 A JP1478278 A JP 1478278A JP 1478278 A JP1478278 A JP 1478278A JP S54107636 A JPS54107636 A JP S54107636A
Authority
JP
Japan
Prior art keywords
card
memory
memory card
address
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1478278A
Other languages
Japanese (ja)
Other versions
JPS579154B2 (en
Inventor
Toshishige Tamura
Norio Inui
Mitsumasa Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1478278A priority Critical patent/JPS54107636A/en
Publication of JPS54107636A publication Critical patent/JPS54107636A/en
Publication of JPS579154B2 publication Critical patent/JPS579154B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0669—Configuration or reconfiguration with decentralised address assignment
    • G06F12/0676—Configuration or reconfiguration with decentralised address assignment the address being position dependent

Abstract

PURPOSE:To make easy the extension of memory cards of various capacity, by constituting each memory card that the address adding the memory capacity of the memory card itself is delivered to the memory card of next stage. CONSTITUTION:The card address set information is fed to the memory card No.1 via the line 6, and it is set to the card address set circuit 2. The content of the set circuit 2 and the memory capacity of the memory card No.1 are added with the addition circuit 3, and the result is fed to the next memory card No.2, setting the card address set circuit 2. In the memory card No.2, the result of addition between the content of the card address set circuit 2 and the memory capacity of the memory card No.2 is delivered to the memory card No.3. Similarly, the card address is set to the card address set circuit of the memory card sequentially.
JP1478278A 1978-02-10 1978-02-10 Address selection method for memory unit Granted JPS54107636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1478278A JPS54107636A (en) 1978-02-10 1978-02-10 Address selection method for memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1478278A JPS54107636A (en) 1978-02-10 1978-02-10 Address selection method for memory unit

Publications (2)

Publication Number Publication Date
JPS54107636A true JPS54107636A (en) 1979-08-23
JPS579154B2 JPS579154B2 (en) 1982-02-19

Family

ID=11870613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1478278A Granted JPS54107636A (en) 1978-02-10 1978-02-10 Address selection method for memory unit

Country Status (1)

Country Link
JP (1) JPS54107636A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6274137A (en) * 1985-09-27 1987-04-04 Oki Electric Ind Co Ltd Memory address setting system
JPH01184559A (en) * 1988-01-19 1989-07-24 Nec Corp System for constituting automatic memory system
JPH01184557A (en) * 1988-01-19 1989-07-24 Nec Corp System for discriminating memory capacity

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51116629A (en) * 1975-04-07 1976-10-14 Hitachi Ltd Memory system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51116629A (en) * 1975-04-07 1976-10-14 Hitachi Ltd Memory system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6274137A (en) * 1985-09-27 1987-04-04 Oki Electric Ind Co Ltd Memory address setting system
JPH0410101B2 (en) * 1985-09-27 1992-02-24
JPH01184559A (en) * 1988-01-19 1989-07-24 Nec Corp System for constituting automatic memory system
JPH01184557A (en) * 1988-01-19 1989-07-24 Nec Corp System for discriminating memory capacity

Also Published As

Publication number Publication date
JPS579154B2 (en) 1982-02-19

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