JPS57113668A - Data detecting signal forming system - Google Patents

Data detecting signal forming system

Info

Publication number
JPS57113668A
JPS57113668A JP55188273A JP18827380A JPS57113668A JP S57113668 A JPS57113668 A JP S57113668A JP 55188273 A JP55188273 A JP 55188273A JP 18827380 A JP18827380 A JP 18827380A JP S57113668 A JPS57113668 A JP S57113668A
Authority
JP
Japan
Prior art keywords
cnt
data
signal
mark
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55188273A
Other languages
Japanese (ja)
Inventor
Osamu Yoshida
Kunio Nozawa
Hajime Kakehi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55188273A priority Critical patent/JPS57113668A/en
Publication of JPS57113668A publication Critical patent/JPS57113668A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To easily cope with the change in data type with increased accuracy of a data detection signal, by generating the data detection signal at first after a data input is counted for a specified count at a counter. CONSTITUTION:A counter CNT is preset to a time corresponding to the pulse width of a mark signal ahead a data signal DT. When the data signal DT is inputted, the CNT starts counting by detecting the mark signal. Since the leading edge of the mark of the data signal DT is dependent on noise, if the CNT decreases before the CNT counts to a preset value, the CNT makes down-count. When the count value of the CNT is zero, the output of a gate G3 is at ''H'' to initialize the circuit. When the CNT counts up to the preset value, a flip-flop FF2 is set and a data detection signal CD is outputted.
JP55188273A 1980-12-29 1980-12-29 Data detecting signal forming system Pending JPS57113668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188273A JPS57113668A (en) 1980-12-29 1980-12-29 Data detecting signal forming system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188273A JPS57113668A (en) 1980-12-29 1980-12-29 Data detecting signal forming system

Publications (1)

Publication Number Publication Date
JPS57113668A true JPS57113668A (en) 1982-07-15

Family

ID=16220774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188273A Pending JPS57113668A (en) 1980-12-29 1980-12-29 Data detecting signal forming system

Country Status (1)

Country Link
JP (1) JPS57113668A (en)

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