JPS57109078A - Multiple computer system - Google Patents
Multiple computer systemInfo
- Publication number
- JPS57109078A JPS57109078A JP55185914A JP18591480A JPS57109078A JP S57109078 A JPS57109078 A JP S57109078A JP 55185914 A JP55185914 A JP 55185914A JP 18591480 A JP18591480 A JP 18591480A JP S57109078 A JPS57109078 A JP S57109078A
- Authority
- JP
- Japan
- Prior art keywords
- systems
- computer
- computer system
- computer systems
- detecting circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To improve the reliability of computer systems by synthronizing those systems with each other by providing each computer system with an oscillating circuit and by supplying a mutual clock signal to each processor at need. CONSTITUTION:Computer systems 11 and 12 constituting a multiple computer system are provided with oscillators 11b and 12b each generating a clock signal, processors 11a and 12a, and fault detecting circuits 11c and 12c. Those detecting circuits 11c and 12c monitor the operation of the whole computer system, and pieces of information on in-use and stand-by modes are inputted to the processors 11a and 12a all the time, so that the detecting circuits 11c and 12c prevent both the computer systems 11 and 12 from serving as in-use systems simultaneously. When the processor 11a or 12a is the in-use system, it operates synchronizing with the clock of the oscillator 11a or 12a of its system and when the stand-by system, it operates synchronizing with the clock of the oscillator 11a or 12a of the other system, thus syncrhonizing the computer systems 11 and 12 with each other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55185914A JPS57109078A (en) | 1980-12-26 | 1980-12-26 | Multiple computer system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55185914A JPS57109078A (en) | 1980-12-26 | 1980-12-26 | Multiple computer system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57109078A true JPS57109078A (en) | 1982-07-07 |
Family
ID=16179082
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55185914A Pending JPS57109078A (en) | 1980-12-26 | 1980-12-26 | Multiple computer system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57109078A (en) |
-
1980
- 1980-12-26 JP JP55185914A patent/JPS57109078A/en active Pending
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