JPS5597652A - Clock monitor system - Google Patents

Clock monitor system

Info

Publication number
JPS5597652A
JPS5597652A JP524379A JP524379A JPS5597652A JP S5597652 A JPS5597652 A JP S5597652A JP 524379 A JP524379 A JP 524379A JP 524379 A JP524379 A JP 524379A JP S5597652 A JPS5597652 A JP S5597652A
Authority
JP
Japan
Prior art keywords
clock
detection circuit
circuit
output
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP524379A
Other languages
Japanese (ja)
Other versions
JPS6213697B2 (en
Inventor
Takeo Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP524379A priority Critical patent/JPS5597652A/en
Publication of JPS5597652A publication Critical patent/JPS5597652A/en
Publication of JPS6213697B2 publication Critical patent/JPS6213697B2/ja
Granted legal-status Critical Current

Links

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To secure the display of the clock fault with every package for the user by providing the detection circuit to confirm the normalcy of the clock plus the circuit to give the test to the operation of the detection circuit to each logic circuit package of the information processor.
CONSTITUTION: With supply of the clock of cycle T to the clock detection circuit provided in each logic package of the information processor, T1<T2<T<T3<T1+ T is secured when the delay time is referred to as T1, T2 and T3 for terminals C1, C2 and C3 each of delay circuit D1. And the output of logic gates G1WG3 caused by the output of FF (A, B) are all 0 if the clock is supplied along with the output of gate G4 featuring also 0. Thus no fault occurring is shown. If the clock is fixed to 0 or 1 due to occurrence of the fault, output "1" is delivered through gate G4 to display the fault occurrence. And at the same time, the test circuit selects 1 or 0 as the test data in case the test is given to the clock detection circuit and then supplies it to the clock detection circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP524379A 1979-01-19 1979-01-19 Clock monitor system Granted JPS5597652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP524379A JPS5597652A (en) 1979-01-19 1979-01-19 Clock monitor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP524379A JPS5597652A (en) 1979-01-19 1979-01-19 Clock monitor system

Publications (2)

Publication Number Publication Date
JPS5597652A true JPS5597652A (en) 1980-07-25
JPS6213697B2 JPS6213697B2 (en) 1987-03-28

Family

ID=11605752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP524379A Granted JPS5597652A (en) 1979-01-19 1979-01-19 Clock monitor system

Country Status (1)

Country Link
JP (1) JPS5597652A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846451A (en) * 1981-09-14 1983-03-17 Fujitsu Ltd Detection processing system for runaway of program
JPS61125959A (en) * 1984-11-22 1986-06-13 株式会社ダイフク Self-propelling car for conveying load
JP2017097629A (en) * 2015-11-25 2017-06-01 日立オートモティブシステムズ株式会社 On-vehicle control device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846451A (en) * 1981-09-14 1983-03-17 Fujitsu Ltd Detection processing system for runaway of program
JPS61125959A (en) * 1984-11-22 1986-06-13 株式会社ダイフク Self-propelling car for conveying load
JPH043341B2 (en) * 1984-11-22 1992-01-22
JP2017097629A (en) * 2015-11-25 2017-06-01 日立オートモティブシステムズ株式会社 On-vehicle control device

Also Published As

Publication number Publication date
JPS6213697B2 (en) 1987-03-28

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