JPS57109025A - Interface controlling system - Google Patents

Interface controlling system

Info

Publication number
JPS57109025A
JPS57109025A JP18616280A JP18616280A JPS57109025A JP S57109025 A JPS57109025 A JP S57109025A JP 18616280 A JP18616280 A JP 18616280A JP 18616280 A JP18616280 A JP 18616280A JP S57109025 A JPS57109025 A JP S57109025A
Authority
JP
Japan
Prior art keywords
adapter
data transfer
devices
controlling system
cpu2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18616280A
Other languages
Japanese (ja)
Inventor
Kazumi Yotsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18616280A priority Critical patent/JPS57109025A/en
Publication of JPS57109025A publication Critical patent/JPS57109025A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To decrease the number of common buses by providing an adapter with a mode switching function and by performing data transfer among channel devices, a CPU and a service processor on a time-division mode by the function. CONSTITUTION:An adapter 4' is provided among a service processor 1, a CPU2, and channel devices 3'-1-3'-n. This adapter 4' selectively switches data transfer modes between the processor 1 and devices 3'-1-3'-n, and data transfer modes between the CPU2 and devices 3'-1-3'-n on a time-division mode. Consequently, the number of common buses is decreased.
JP18616280A 1980-12-26 1980-12-26 Interface controlling system Pending JPS57109025A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18616280A JPS57109025A (en) 1980-12-26 1980-12-26 Interface controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18616280A JPS57109025A (en) 1980-12-26 1980-12-26 Interface controlling system

Publications (1)

Publication Number Publication Date
JPS57109025A true JPS57109025A (en) 1982-07-07

Family

ID=16183465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18616280A Pending JPS57109025A (en) 1980-12-26 1980-12-26 Interface controlling system

Country Status (1)

Country Link
JP (1) JPS57109025A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63266567A (en) * 1987-04-24 1988-11-02 Hitachi Ltd Input/output circuit
EP2309395A1 (en) * 2008-07-31 2011-04-13 Actions Semiconductor Co., Ltd. Method for realizing pins time share multiplexing and a system-on-a-chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63266567A (en) * 1987-04-24 1988-11-02 Hitachi Ltd Input/output circuit
EP2309395A1 (en) * 2008-07-31 2011-04-13 Actions Semiconductor Co., Ltd. Method for realizing pins time share multiplexing and a system-on-a-chip
EP2309395A4 (en) * 2008-07-31 2011-08-31 Actions Semiconductor Co Ltd Method for realizing pins time share multiplexing and a system-on-a-chip

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