JPS57108937A - Trap system by instruction code - Google Patents

Trap system by instruction code

Info

Publication number
JPS57108937A
JPS57108937A JP55184747A JP18474780A JPS57108937A JP S57108937 A JPS57108937 A JP S57108937A JP 55184747 A JP55184747 A JP 55184747A JP 18474780 A JP18474780 A JP 18474780A JP S57108937 A JPS57108937 A JP S57108937A
Authority
JP
Japan
Prior art keywords
instruction
code
instruction code
trapped
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55184747A
Other languages
Japanese (ja)
Inventor
Toshio Oma
Yasushi Tokunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP55184747A priority Critical patent/JPS57108937A/en
Publication of JPS57108937A publication Critical patent/JPS57108937A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To eliminate the trouble in checking all of addresses of instructions to be trapped by automatically selecting instructions to be trapped which are included in a program to be tested, and by performing trap processing. CONSTITUTION:Each instruction (ai) is stored in the address (i) of the memory 6 of a stored-program control type processor. An instruction code (c) for specifying the kind of an instruction to be trapped is set in an instruction trap register 2, and a mask code (m) for specifying the digit of the instruction (ai) to be compared with the instruction code (c) is set in a mask register 3. Each instruction (ai) is read out of the memory 6 and stored in an instruction register 1 every time execution is performed. The (ai) is multiplied logically by the mask code (m) to extract an instruction code correspondence part (ami). The instruction code correspondence part (ami) is compared with the instruction code (c) by a coincidence circuit 5, which when the both are coincident with each other, outputs a coincidence detection signal (t).
JP55184747A 1980-12-25 1980-12-25 Trap system by instruction code Pending JPS57108937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55184747A JPS57108937A (en) 1980-12-25 1980-12-25 Trap system by instruction code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55184747A JPS57108937A (en) 1980-12-25 1980-12-25 Trap system by instruction code

Publications (1)

Publication Number Publication Date
JPS57108937A true JPS57108937A (en) 1982-07-07

Family

ID=16158630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55184747A Pending JPS57108937A (en) 1980-12-25 1980-12-25 Trap system by instruction code

Country Status (1)

Country Link
JP (1) JPS57108937A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005076137A1 (en) * 2004-02-05 2005-08-18 Research In Motion Limited Memory controller interface

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005076137A1 (en) * 2004-02-05 2005-08-18 Research In Motion Limited Memory controller interface
US7610433B2 (en) 2004-02-05 2009-10-27 Research In Motion Limited Memory controller interface
US8086788B2 (en) 2004-02-05 2011-12-27 Research In Motion Limited Memory controller interface
US8347025B2 (en) 2004-02-05 2013-01-01 Research In Motion Limited Memory controller interface

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