JPS57106937A - Prefetch controller - Google Patents

Prefetch controller

Info

Publication number
JPS57106937A
JPS57106937A JP55183180A JP18318080A JPS57106937A JP S57106937 A JPS57106937 A JP S57106937A JP 55183180 A JP55183180 A JP 55183180A JP 18318080 A JP18318080 A JP 18318080A JP S57106937 A JPS57106937 A JP S57106937A
Authority
JP
Japan
Prior art keywords
data
register
address
specified
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55183180A
Other languages
Japanese (ja)
Inventor
Masahiro Kawakatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55183180A priority Critical patent/JPS57106937A/en
Publication of JPS57106937A publication Critical patent/JPS57106937A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To execute a sequence of commands within the time of each gap between high-density records, by prefetching the data of a main storage device, specified by a specific address register, in a buffer register. CONSTITUTION:Data of a main storage device MS specified by a specific address register among address registers LS for access to the main storage device MS is prefetched into a buffer register MSDBR, and the address of the data in the MS is held in a register DBMSAR. When a specific register, e.g., LS1 is specified by an address LSA from a channel device, access signals LS and AC from a decoder DEC are applied to a gate G1 and a prefetching circuit PFC, and a comparator COMP compares the contents of the DBMSAR with those of the LS1. When both of them are coincident with each other, a gate G2 is opened to output the data of the MSDBR to a bus DB. Therefore, said operation is performed faster than the fetching of the data from the MS, and no command overrun is caused even in a short gap between records.
JP55183180A 1980-12-24 1980-12-24 Prefetch controller Pending JPS57106937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55183180A JPS57106937A (en) 1980-12-24 1980-12-24 Prefetch controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55183180A JPS57106937A (en) 1980-12-24 1980-12-24 Prefetch controller

Publications (1)

Publication Number Publication Date
JPS57106937A true JPS57106937A (en) 1982-07-03

Family

ID=16131166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55183180A Pending JPS57106937A (en) 1980-12-24 1980-12-24 Prefetch controller

Country Status (1)

Country Link
JP (1) JPS57106937A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256455A (en) * 1985-05-06 1986-11-14 ウオング・ラボラトリ−ズ・インコ−ポレ−テツド Information processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256455A (en) * 1985-05-06 1986-11-14 ウオング・ラボラトリ−ズ・インコ−ポレ−テツド Information processing system

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