JPS57106256A - Synchronizing system - Google Patents

Synchronizing system

Info

Publication number
JPS57106256A
JPS57106256A JP55182460A JP18246080A JPS57106256A JP S57106256 A JPS57106256 A JP S57106256A JP 55182460 A JP55182460 A JP 55182460A JP 18246080 A JP18246080 A JP 18246080A JP S57106256 A JPS57106256 A JP S57106256A
Authority
JP
Japan
Prior art keywords
synchronizing
bits
phase
speed
synchronizing signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55182460A
Other languages
Japanese (ja)
Inventor
Kyoji Koseki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55182460A priority Critical patent/JPS57106256A/en
Publication of JPS57106256A publication Critical patent/JPS57106256A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To enhance practically the speed of the synchronizing processing in the receiving side to accelerate the communication speed, by dividing a synchronizing signal into an optional number of phases and by transmitting them. CONSTITUTION:A synchronizing signal is divided into four phases and the synchronizing pattern of each phase includes signals of each phase in every 4 bits. in the receiving side, the number of phase shift bits of each synchronizing pattern is detected to discriminate the phase, and a frame synchronizing point is determined. At this time, the speed of the receiving synchronizing pattern is the 1/4 of the transmission speed. In this case, a CPU1 fetches every 8 or 7 bits of data which are sampled from receiving data RD at every 4 bits and are stored in a shift register 3 and discriminates the synchronizing signal, and simultaneously, the value of phase shift determined by discrimination of the synchronizing signal is preset to a counter 6, and the CPU1 is interrupted by the end of the count to receive following data.
JP55182460A 1980-12-22 1980-12-22 Synchronizing system Pending JPS57106256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55182460A JPS57106256A (en) 1980-12-22 1980-12-22 Synchronizing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182460A JPS57106256A (en) 1980-12-22 1980-12-22 Synchronizing system

Publications (1)

Publication Number Publication Date
JPS57106256A true JPS57106256A (en) 1982-07-02

Family

ID=16118651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182460A Pending JPS57106256A (en) 1980-12-22 1980-12-22 Synchronizing system

Country Status (1)

Country Link
JP (1) JPS57106256A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61239740A (en) * 1985-04-17 1986-10-25 Hitachi Ltd Synchronous signal detecting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61239740A (en) * 1985-04-17 1986-10-25 Hitachi Ltd Synchronous signal detecting device

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