JPS56147215A - Set system for initial value - Google Patents

Set system for initial value

Info

Publication number
JPS56147215A
JPS56147215A JP5065180A JP5065180A JPS56147215A JP S56147215 A JPS56147215 A JP S56147215A JP 5065180 A JP5065180 A JP 5065180A JP 5065180 A JP5065180 A JP 5065180A JP S56147215 A JPS56147215 A JP S56147215A
Authority
JP
Japan
Prior art keywords
initial value
devices
value setting
rom3
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5065180A
Other languages
Japanese (ja)
Inventor
Ryoichi Mazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5065180A priority Critical patent/JPS56147215A/en
Publication of JPS56147215A publication Critical patent/JPS56147215A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To set the initial value to the storage device with a simple constitution, by connecting plural storage devices of independent operations in series to form a shift register and by inputting and shifting initial value setting data from the ROM. CONSTITUTION:At the initial value setting time, storage devices (FFs) 4-9 which operate independently normally are connected in series by the data line to form a shift register. Initial value 1 or 0 for devices 4-9 is set preliminarily in ROM3 of initial value setting data mechanism 1. Counter 2 of mechanism 1 has a function to count up the number of devices 4-9 and stop counting after that. The initial value setting operation is started by signal R, and counter 2 counts closk pulses T, and FFs operate as the shift register by signal G. Counter 2 outputs address signals A0-A2 to ROM3 in accordance with the count of clocks, and ROM3 reads initial set values of devices 4-9 successively in accordance with these signals and performs the shift operation of devices 4-9 to input initial values to respective storage devices.
JP5065180A 1980-04-17 1980-04-17 Set system for initial value Pending JPS56147215A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5065180A JPS56147215A (en) 1980-04-17 1980-04-17 Set system for initial value

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5065180A JPS56147215A (en) 1980-04-17 1980-04-17 Set system for initial value

Publications (1)

Publication Number Publication Date
JPS56147215A true JPS56147215A (en) 1981-11-16

Family

ID=12864835

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5065180A Pending JPS56147215A (en) 1980-04-17 1980-04-17 Set system for initial value

Country Status (1)

Country Link
JP (1) JPS56147215A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175831A (en) * 1989-12-05 1992-12-29 Zilog, Inc. System register initialization technique employing a non-volatile/read only memory
US5230058A (en) * 1989-12-05 1993-07-20 Zilog, Inc. IC chip having volatile memory cells simultaneously loaded with initialization data from uniquely associated non-volatile memory cells via switching transistors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175831A (en) * 1989-12-05 1992-12-29 Zilog, Inc. System register initialization technique employing a non-volatile/read only memory
US5230058A (en) * 1989-12-05 1993-07-20 Zilog, Inc. IC chip having volatile memory cells simultaneously loaded with initialization data from uniquely associated non-volatile memory cells via switching transistors

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