JPS57103546A - Baud rate setting system - Google Patents

Baud rate setting system

Info

Publication number
JPS57103546A
JPS57103546A JP55179367A JP17936780A JPS57103546A JP S57103546 A JPS57103546 A JP S57103546A JP 55179367 A JP55179367 A JP 55179367A JP 17936780 A JP17936780 A JP 17936780A JP S57103546 A JPS57103546 A JP S57103546A
Authority
JP
Japan
Prior art keywords
baud rate
code
teletypewriter
clock signal
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55179367A
Other languages
Japanese (ja)
Inventor
Masae Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55179367A priority Critical patent/JPS57103546A/en
Publication of JPS57103546A publication Critical patent/JPS57103546A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To realize the automatic setting of a baud rate, by converting a character code into a parallel code by the clock signal which is set to a baud rate generator and then delivered and then reading the parallel code by a microcomputer. CONSTITUTION:A start bit ST of the code transmitted from a teletypewriter connected to an RS-232-C interface 1 of the EIA standard is supplied to a counter 2. Thus the counter 2 is operated by a clock signal 6 to perform counting for a section of logic 0 of the bit ST. In other words, the 1-bit length of the ST is equivalent to the baud rate of the teletypewriter. Accordingly, the data of the 1-bit length is set as it is to a baud rate generator 3 by a microcomputer 8. Thus an output clock signal 5 indicates the baud rate of the teletypewriter. Then the character code which is supplied in series to a communication interface 4 is converted into a parallel code by the signal 5 to be read by the computer 8.
JP55179367A 1980-12-18 1980-12-18 Baud rate setting system Pending JPS57103546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55179367A JPS57103546A (en) 1980-12-18 1980-12-18 Baud rate setting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55179367A JPS57103546A (en) 1980-12-18 1980-12-18 Baud rate setting system

Publications (1)

Publication Number Publication Date
JPS57103546A true JPS57103546A (en) 1982-06-28

Family

ID=16064608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55179367A Pending JPS57103546A (en) 1980-12-18 1980-12-18 Baud rate setting system

Country Status (1)

Country Link
JP (1) JPS57103546A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0281307A2 (en) * 1987-03-02 1988-09-07 AT&T Corp. Asynchronous interface and method for coupling data between a data module and a serial asynchronous peripheral
DE4308418A1 (en) * 1993-03-17 1994-09-22 Elsa Gmbh Bit rate detection
US6434659B1 (en) 1993-06-25 2002-08-13 Hitachi, Ltd. Microcomputer having a non-volatile semiconductor memory having a first block storing a program and a second block for storing data which is selectively erased under predetermined conditions if data is found written in that block

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0281307A2 (en) * 1987-03-02 1988-09-07 AT&T Corp. Asynchronous interface and method for coupling data between a data module and a serial asynchronous peripheral
DE4308418A1 (en) * 1993-03-17 1994-09-22 Elsa Gmbh Bit rate detection
WO1994022252A1 (en) 1993-03-17 1994-09-29 Elsa Gmbh Bit rate recognition
US5631925A (en) * 1993-03-17 1997-05-20 Elsa Gmbh Bit rate detection
US6434659B1 (en) 1993-06-25 2002-08-13 Hitachi, Ltd. Microcomputer having a non-volatile semiconductor memory having a first block storing a program and a second block for storing data which is selectively erased under predetermined conditions if data is found written in that block

Similar Documents

Publication Publication Date Title
JPS5570783A (en) Sound information clock
JPS57103546A (en) Baud rate setting system
JPS52128024A (en) Binal data coding method
JPS57197961A (en) Conversion system for image data
JPS5525291A (en) Serial data transmission device
JPS55156486A (en) Information supply system
JPS5429534A (en) Adding system of optional functions to composite terminal
JPS57150035A (en) Code converting circuit system
JPS5462740A (en) Input-output controller
JPS5683163A (en) Encoding system
JPS54122008A (en) Data transmission system
JPS57190445A (en) Transfer speed setting system
JPS5525292A (en) Data reception device
JPS547254A (en) Digital electronic apparatus
JPS5595155A (en) Operation check system for counter
JPS54126006A (en) Information service device
JPS5372540A (en) Interface circuit
JPS57133783A (en) Slice level setting system
JPS5299029A (en) Input/output interface control system
JPS57157621A (en) Digital error generating circuit
JPS5640346A (en) Data transmission system
JPS5679546A (en) Data transmission system
JPS53126231A (en) Interface control system
JPS56131243A (en) Control signal inserting method
JPS5338929A (en) Intermittent signal output method and device