JPS5462740A - Input-output controller - Google Patents

Input-output controller

Info

Publication number
JPS5462740A
JPS5462740A JP12878077A JP12878077A JPS5462740A JP S5462740 A JPS5462740 A JP S5462740A JP 12878077 A JP12878077 A JP 12878077A JP 12878077 A JP12878077 A JP 12878077A JP S5462740 A JPS5462740 A JP S5462740A
Authority
JP
Japan
Prior art keywords
status
signal
output
mode
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12878077A
Other languages
Japanese (ja)
Inventor
Shigemi Mio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12878077A priority Critical patent/JPS5462740A/en
Publication of JPS5462740A publication Critical patent/JPS5462740A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to make a connection to a channel in any operation mode, by equipping an operation-mode discriminating method for channel.
CONSTITUTION: The NOT output of NOT between signalsof status bits 0 to 7 becomes the status of (00)16. The output of AND between the status signal of (00)16 an and initial selective sequence signal, status-in signal and service-out signal becomes the status announcement point of (00)16 at the time of the initial selective sequence. By inputting this AND signal to trigger inpout terminal T of the D type FF and a hold-out signal to data input terminal D, the appearance of output "1" at its positive output terminal Q indicates a burst mode, and output "1" at negative output terminal -Q indicates a byte mode. In this way, the inputoutput control is done accroding to the discriminated operation mode, so that the connection to a channel in any operation mode can be made freely.
COPYRIGHT: (C)1979,JPO&Japio
JP12878077A 1977-10-28 1977-10-28 Input-output controller Pending JPS5462740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12878077A JPS5462740A (en) 1977-10-28 1977-10-28 Input-output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12878077A JPS5462740A (en) 1977-10-28 1977-10-28 Input-output controller

Publications (1)

Publication Number Publication Date
JPS5462740A true JPS5462740A (en) 1979-05-21

Family

ID=14993268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12878077A Pending JPS5462740A (en) 1977-10-28 1977-10-28 Input-output controller

Country Status (1)

Country Link
JP (1) JPS5462740A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5629732A (en) * 1979-08-20 1981-03-25 Nec Corp Bus control system
JPS57197629A (en) * 1981-05-30 1982-12-03 Nec Corp Data transferring system
JPS5897730A (en) * 1981-12-07 1983-06-10 Nec Corp Data processor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5629732A (en) * 1979-08-20 1981-03-25 Nec Corp Bus control system
JPS57197629A (en) * 1981-05-30 1982-12-03 Nec Corp Data transferring system
JPH042980B2 (en) * 1981-05-30 1992-01-21
JPS5897730A (en) * 1981-12-07 1983-06-10 Nec Corp Data processor

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