JPS57103450A - Clock extracting circuit - Google Patents

Abstract

PURPOSE:To obtain a light-weight, small-size, and nonadjusting clock extracting circuit, by storing a maximum position detection signal of a return-to-zero single current digital code in a counter, which counts local clocks of a high frequency, to divide the frequency of local clocks. CONSTITUTION:A return-to-zero single current digital code S4 is inputted to a maximum position detecting circuit 1; and when a pulse of the code S4 becomes maximum, a detection signal S5 is transmitted to a storage terminal LD of a counting circuit 3. Local clocks S6 from a local clock generator 2 which generates clocks of an about 8-fold frequency of the clock frequency of the code S4 are inputted to the circuit 3 from a terminal CP and are counted; and when the signal S5 is applied to the circuit 3, the circuit 3 stored 1,0, and 0 from data input terminals D2, D1, and D0. That is, the phase of the circuit 3 is corrected at every maximum point of pulses of the code S4. Consequently, clocks S7 are extracted from an 8 frequency division output Q2 of the circuit 3 and are outputted.