JPS57100686A - Nonvolatile semiconductor memory - Google Patents

Nonvolatile semiconductor memory

Info

Publication number
JPS57100686A
JPS57100686A JP17528880A JP17528880A JPS57100686A JP S57100686 A JPS57100686 A JP S57100686A JP 17528880 A JP17528880 A JP 17528880A JP 17528880 A JP17528880 A JP 17528880A JP S57100686 A JPS57100686 A JP S57100686A
Authority
JP
Japan
Prior art keywords
threshold voltage
row line
selected row
unselected
charged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17528880A
Other languages
Japanese (ja)
Other versions
JPH0318349B2 (en
Inventor
Hiroshi Iwahashi
Masamichi Asano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP17528880A priority Critical patent/JPS57100686A/en
Publication of JPS57100686A publication Critical patent/JPS57100686A/en
Publication of JPH0318349B2 publication Critical patent/JPH0318349B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To increase a process margin by enabling a sufficient high voltage to be applied to a selected row line, by setting the threshold voltage of a protective transistor (TR) to an adequate value higher than the threshold voltage of a load TR. CONSTITUTION:A load TR11 and a protective TR12 are manufactured in different manufacture processes to set the threshold voltage of the TR11 sufficiently low, and the threshold voltage of the TR12 higher than the threshold voltage of the TR11. During reading operation, a selected row line is charged by a power source normally without reference to whether the output terminal N of a row decoder body 10 is selected or not, and unselected row lines are discharged. During writing operation, on the other hand, the TR12 connected to the unselected row line turns on completely and the unselected row lines are discharged to turn off the TR12 connected to the selected row line, so that this selected row line is charged up to a sufficiently high voltage through the TR11 connected to it.
JP17528880A 1980-12-12 1980-12-12 Nonvolatile semiconductor memory Granted JPS57100686A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17528880A JPS57100686A (en) 1980-12-12 1980-12-12 Nonvolatile semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17528880A JPS57100686A (en) 1980-12-12 1980-12-12 Nonvolatile semiconductor memory

Publications (2)

Publication Number Publication Date
JPS57100686A true JPS57100686A (en) 1982-06-22
JPH0318349B2 JPH0318349B2 (en) 1991-03-12

Family

ID=15993490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17528880A Granted JPS57100686A (en) 1980-12-12 1980-12-12 Nonvolatile semiconductor memory

Country Status (1)

Country Link
JP (1) JPS57100686A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4583205A (en) * 1982-09-17 1986-04-15 Nec Corporation Programmable memory circuit with an improved programming voltage applying circuit
FR2582135A1 (en) * 1985-05-14 1986-11-21 Sgs Microelettronica Spa PRELOAD CIRCUIT FOR WORD LINES OF A MEMORY DEVICE, PARTICULARLY WITH PROGRAMMABLE CELLS

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5677980A (en) * 1979-11-26 1981-06-26 Fujitsu Ltd Semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5677980A (en) * 1979-11-26 1981-06-26 Fujitsu Ltd Semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4583205A (en) * 1982-09-17 1986-04-15 Nec Corporation Programmable memory circuit with an improved programming voltage applying circuit
FR2582135A1 (en) * 1985-05-14 1986-11-21 Sgs Microelettronica Spa PRELOAD CIRCUIT FOR WORD LINES OF A MEMORY DEVICE, PARTICULARLY WITH PROGRAMMABLE CELLS

Also Published As

Publication number Publication date
JPH0318349B2 (en) 1991-03-12

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