JPS5443633A - Memory erasing method - Google Patents

Memory erasing method

Info

Publication number
JPS5443633A
JPS5443633A JP11026977A JP11026977A JPS5443633A JP S5443633 A JPS5443633 A JP S5443633A JP 11026977 A JP11026977 A JP 11026977A JP 11026977 A JP11026977 A JP 11026977A JP S5443633 A JPS5443633 A JP S5443633A
Authority
JP
Japan
Prior art keywords
erasing
rated voltage
voltage
value
rated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11026977A
Other languages
Japanese (ja)
Other versions
JPS5727558B2 (en
Inventor
Takeshi Mizusawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11026977A priority Critical patent/JPS5443633A/en
Publication of JPS5443633A publication Critical patent/JPS5443633A/en
Publication of JPS5727558B2 publication Critical patent/JPS5727558B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Landscapes

  • Read Only Memory (AREA)

Abstract

PURPOSE:In the early stage of erasing while a large current flows, an erasing voltage lower than a rated voltage value is applied and increased up to the rated voltage as the current decreases according to the progress of erasing so as to reduce the peak value in the early stage of erasing, thereby erasing several memories power supplies identical in capacity. CONSTITUTION:By applying an erasing voltage to a memory integrated-circuit, memory information in all of memory cells is erased through the avalanche injection of erasing charge into all of cells of the integrated circuit. By the method mentioned above, a Zener diode which becomes conductive by rated voltage VE is connected in parallel at the output side of the rated current supply of IA in value and in the early erasing stage while a large current flows, an erasing voltage lower than rated voltage VE applied to memory cells of the integrated circuit is increased up to rated voltage VE as the current value decreases according to the progress of erasing. In the other way, a current control resistance or the like is connected in series so as to obtain the same effect.
JP11026977A 1977-09-13 1977-09-13 Memory erasing method Granted JPS5443633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11026977A JPS5443633A (en) 1977-09-13 1977-09-13 Memory erasing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11026977A JPS5443633A (en) 1977-09-13 1977-09-13 Memory erasing method

Publications (2)

Publication Number Publication Date
JPS5443633A true JPS5443633A (en) 1979-04-06
JPS5727558B2 JPS5727558B2 (en) 1982-06-11

Family

ID=14531393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11026977A Granted JPS5443633A (en) 1977-09-13 1977-09-13 Memory erasing method

Country Status (1)

Country Link
JP (1) JPS5443633A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61184797A (en) * 1984-08-14 1986-08-18 テキサス　インスツルメンツ　インコ−ポレイテツド Programming of floating gate memory and electrically erasable programmable semiconductor memory cell
US4996571A (en) * 1988-07-08 1991-02-26 Hitachi, Ltd. Non-volatile semiconductor memory device erasing operation
JPH0561720B2 (en) * 1981-09-28 1993-09-06 Motorola Inc

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5993557A (en) * 1982-11-18 1984-05-30 Hiroshi Teramachi Ball screw with central flange and ball screw unit using same
JPS6315615Y2 (en) * 1986-12-25 1988-05-02

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4846230A (en) * 1971-10-14 1973-07-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4846230A (en) * 1971-10-14 1973-07-02

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0561720B2 (en) * 1981-09-28 1993-09-06 Motorola Inc
JPS61184797A (en) * 1984-08-14 1986-08-18 テキサス　インスツルメンツ　インコ−ポレイテツド Programming of floating gate memory and electrically erasable programmable semiconductor memory cell
US4996571A (en) * 1988-07-08 1991-02-26 Hitachi, Ltd. Non-volatile semiconductor memory device erasing operation

Also Published As

Publication number Publication date
JPS5727558B2 (en) 1982-06-11

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