JPS5699554A - Operation log storage device of information processing unit - Google Patents
Operation log storage device of information processing unitInfo
- Publication number
- JPS5699554A JPS5699554A JP147580A JP147580A JPS5699554A JP S5699554 A JPS5699554 A JP S5699554A JP 147580 A JP147580 A JP 147580A JP 147580 A JP147580 A JP 147580A JP S5699554 A JPS5699554 A JP S5699554A
- Authority
- JP
- Japan
- Prior art keywords
- address
- signal
- instruction
- memory part
- operation log
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To enable to easily store the operation log of the instruction without debasing the efficiency, by using the address which has accessed the memory device, and adding ''1'' to the contents of the corresponding address of the log memory part whenever the instruction is output. CONSTITUTION:When a signal (b) for starting the memory device 11 is made ''0'', a chip selective signal (h) to the log memory part 16 becomes ''0'', and the memory part 16 is started. The A address is provided to the address signal (a) of the terminal 12, and the instruction is input to the address A of the device 11, and therefore, a signal (d) of the instruction read-out signal terminal 21 becomes ''1''. Accordingly, a signal (g) which can be written to the memory part from the control part 18 is output from the terminal 27. Also, since an addition approval signal to the adder circuit 17 becomes ''1'', the contents which have been read out from the address A of the memory part 16 are added by ''1'', and are written again to the address A. In this way, frequency of the address to which the instruction has been accessed is stored in the corresponding address of the memory part 16.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP147580A JPS5699554A (en) | 1980-01-09 | 1980-01-09 | Operation log storage device of information processing unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP147580A JPS5699554A (en) | 1980-01-09 | 1980-01-09 | Operation log storage device of information processing unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5699554A true JPS5699554A (en) | 1981-08-10 |
Family
ID=11502472
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP147580A Pending JPS5699554A (en) | 1980-01-09 | 1980-01-09 | Operation log storage device of information processing unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5699554A (en) |
-
1980
- 1980-01-09 JP JP147580A patent/JPS5699554A/en active Pending
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