JPS5698971A - Synchronizing converter - Google Patents

Abstract

PURPOSE:To output a synchronizing conversion signal which can alternately be read out and written in, by taking the logical sum output signal indicating apair of memory readout and write-in period as toggle input for FF, and using two synchronizing signals in which the frequency of synchronizing signals is almost equal and the phase relation is random. CONSTITUTION:Among n sets (where; n is 2 or more positive integer) of TV signals having vertical and horizontal synchronizing signals in which the frequency is almost equal and the phase is random, the signal from timing generators 1a, 1b separately supplied, is selected for the address, to display the synthesized picture and write-in/readout picture in a pair of 2(n-1) sets of memories 4a, 4b. In the write-in and readout, the logical sum between the output signal a of the generator 1a and the output signal b of the generator 1b is taken at the OR circuit 8, and FF7 is toggled with the output signal c of the circuit 8. Further, the outputs Q and Q' of FF7 control the address selectors 5a, 5b and memories 4a, 4b for alternate write-in and readout operation.