JPS5662423A - Ad converter - Google Patents

Ad converter

Info

Publication number
JPS5662423A
JPS5662423A JP14011079A JP14011079A JPS5662423A JP S5662423 A JPS5662423 A JP S5662423A JP 14011079 A JP14011079 A JP 14011079A JP 14011079 A JP14011079 A JP 14011079A JP S5662423 A JPS5662423 A JP S5662423A
Authority
JP
Japan
Prior art keywords
content
memory circuit
decoder
circuit groups
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14011079A
Other languages
Japanese (ja)
Inventor
Toshiyuki Ozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP14011079A priority Critical patent/JPS5662423A/en
Publication of JPS5662423A publication Critical patent/JPS5662423A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/20—Cathode-ray oscilloscopes
    • G01R13/22—Circuits therefor
    • G01R13/28—Circuits for simultaneous or sequential presentation of more than one variable

Abstract

PURPOSE:To process two different signals, by using an AD converter and a decoder in time sharing in common. CONSTITUTION:In case of the use as a peak hold meter, left and right channel signals are respectively fed to the 1st and second input terminals 1, 2. Each signal is alternately in AD conversion in time sharing and stored respectively in memory circuits 4 and 5. The content of the memory circuit groups, 4, 5 is compared with the content stored in the memory circuit groups 6 and 7, and if the content of the former is greater than that of the latter, the content of the former is written in the latter. That is, the peak of data input to the memory circuit groups 4, 5 is held in the memory circuit groups 6 and 7. The content of the memory circuit groups 6 and 7. The content of the memory circuit group 6 is decoded at the decoder 9 during the 1st timing signal period, the this content and that of the decoder 8 are synthesized at the decoder 10 and displayed on a display group 12. Similarly, they are displayed on a display circuit group 13 during the 2nd timing period.
JP14011079A 1979-10-29 1979-10-29 Ad converter Pending JPS5662423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14011079A JPS5662423A (en) 1979-10-29 1979-10-29 Ad converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14011079A JPS5662423A (en) 1979-10-29 1979-10-29 Ad converter

Publications (1)

Publication Number Publication Date
JPS5662423A true JPS5662423A (en) 1981-05-28

Family

ID=15261152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14011079A Pending JPS5662423A (en) 1979-10-29 1979-10-29 Ad converter

Country Status (1)

Country Link
JP (1) JPS5662423A (en)

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