JPS569851A - Error information report processing system - Google Patents

Error information report processing system

Info

Publication number
JPS569851A
JPS569851A JP8539979A JP8539979A JPS569851A JP S569851 A JPS569851 A JP S569851A JP 8539979 A JP8539979 A JP 8539979A JP 8539979 A JP8539979 A JP 8539979A JP S569851 A JPS569851 A JP S569851A
Authority
JP
Japan
Prior art keywords
unit
address
error
write
bia
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8539979A
Other languages
Japanese (ja)
Other versions
JPS598851B2 (en
Inventor
Akira Hattori
Kazuyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54085399A priority Critical patent/JPS598851B2/en
Publication of JPS569851A publication Critical patent/JPS569851A/en
Publication of JPS598851B2 publication Critical patent/JPS598851B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to process an error by making a reproduction of a write address having been lost, by reporting an error address in write error generation by making use of a buffer invalidation address bus.
CONSTITUTION: Once access requesting original unit 1-0 sends a write request, memory access controller 2 accepts the request and starts write operation for memory 3 and at the same time, unit 2 transfers buffer invalidation address BIA to other access requesting original units 1-1W1-3. Next, since unit 2 never transfers BIA to unit 1-0 at this timing, the attention is paid to this to let unit 2 report [write-error-possible address] to unit 1-0 via BIA bus 6-0. Then, the possible address is held in unit 1-0 and when unit 2 generates an error in write operation actually, the generation is reported to unit 1-0. When no error occurs, the held possible address is erased.
COPYRIGHT: (C)1981,JPO&Japio
JP54085399A 1979-07-05 1979-07-05 Error information notification processing method Expired JPS598851B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54085399A JPS598851B2 (en) 1979-07-05 1979-07-05 Error information notification processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54085399A JPS598851B2 (en) 1979-07-05 1979-07-05 Error information notification processing method

Publications (2)

Publication Number Publication Date
JPS569851A true JPS569851A (en) 1981-01-31
JPS598851B2 JPS598851B2 (en) 1984-02-28

Family

ID=13857693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54085399A Expired JPS598851B2 (en) 1979-07-05 1979-07-05 Error information notification processing method

Country Status (1)

Country Link
JP (1) JPS598851B2 (en)

Also Published As

Publication number Publication date
JPS598851B2 (en) 1984-02-28

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