JPS5476023A - Error correction system for tag memory - Google Patents

Error correction system for tag memory

Info

Publication number
JPS5476023A
JPS5476023A JP14340977A JP14340977A JPS5476023A JP S5476023 A JPS5476023 A JP S5476023A JP 14340977 A JP14340977 A JP 14340977A JP 14340977 A JP14340977 A JP 14340977A JP S5476023 A JPS5476023 A JP S5476023A
Authority
JP
Japan
Prior art keywords
memory
control information
region
tag
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14340977A
Other languages
Japanese (ja)
Inventor
Akira Hattori
Yukio Soma
Takamitsu Tsuchimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14340977A priority Critical patent/JPS5476023A/en
Publication of JPS5476023A publication Critical patent/JPS5476023A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To secure the error correction for the tag memory without lowering the speed by reading the necessary data from the tag copy holding region provided newly in case some error is detected.
CONSTITUTION: In the case of NOT FOUND, that is, when the requested data does not exist in buffer memory 4 and 5, the way number designated by replacement circuit 9 as well as the address information are sent to main memory 1. Memory 1 renews tag copy holding region 2. (The higher addresses of the address information are written into the corresponding control information memory region at region 2.) At the same time, the original MOVE IN action is carried out. Then in case the parity error is detected (6-1W6-4) in the control information read from tag 5, the way number is informed to memory to memory 1 for the control information to which the set address and error are detected. Memory 1 reads out the corresponding control information from region 2, and the information is transferred to memory 4 and 5 to be then sent to comparator 8-i via selector 7-i. Thus, the access process is continued.
COPYRIGHT: (C)1979,JPO&Japio
JP14340977A 1977-11-30 1977-11-30 Error correction system for tag memory Pending JPS5476023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14340977A JPS5476023A (en) 1977-11-30 1977-11-30 Error correction system for tag memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14340977A JPS5476023A (en) 1977-11-30 1977-11-30 Error correction system for tag memory

Publications (1)

Publication Number Publication Date
JPS5476023A true JPS5476023A (en) 1979-06-18

Family

ID=15338091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14340977A Pending JPS5476023A (en) 1977-11-30 1977-11-30 Error correction system for tag memory

Country Status (1)

Country Link
JP (1) JPS5476023A (en)

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