JPS569844A - Instruction fetch processing system - Google Patents

Instruction fetch processing system

Info

Publication number
JPS569844A
JPS569844A JP8540079A JP8540079A JPS569844A JP S569844 A JPS569844 A JP S569844A JP 8540079 A JP8540079 A JP 8540079A JP 8540079 A JP8540079 A JP 8540079A JP S569844 A JPS569844 A JP S569844A
Authority
JP
Japan
Prior art keywords
instruction
buffer
resides
cpu4
instruction fetch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8540079A
Other languages
Japanese (ja)
Inventor
Yasushi Ikeda
Isao Aizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8540079A priority Critical patent/JPS569844A/en
Publication of JPS569844A publication Critical patent/JPS569844A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To increase a processing speed on the whole by discriminating and sending an instruction fetch request, corresponding to whether an instruction to be executed next resides on an instruction buffer, to a buffer memory side.
CONSTITUTION: The processing system consists of main memory unit 1, buffer memory part 2, buffer memory controller 3, CPU4 and instruction buffer 5. Depending upon whether an instruction to be executed next resides on buffer 5 when CPU4 starts instruction prefetch operation and one-cycle operation, CPU4 sends different instruction fetch requests. Namely, when it resides, the 1st instruction fetch request IPFREQ is sent out and when not, the 2nd instruction fetch request IFREQ is sent out. Unit 3 having received request IPFREQ, when a desired instruction to be prefetched resides on memory 2, reads it to send instruction end signal IEND to CPU4 and also to transfer it to buffer 5.
COPYRIGHT: (C)1981,JPO&Japio
JP8540079A 1979-07-05 1979-07-05 Instruction fetch processing system Pending JPS569844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8540079A JPS569844A (en) 1979-07-05 1979-07-05 Instruction fetch processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8540079A JPS569844A (en) 1979-07-05 1979-07-05 Instruction fetch processing system

Publications (1)

Publication Number Publication Date
JPS569844A true JPS569844A (en) 1981-01-31

Family

ID=13857724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8540079A Pending JPS569844A (en) 1979-07-05 1979-07-05 Instruction fetch processing system

Country Status (1)

Country Link
JP (1) JPS569844A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6356731A (en) * 1986-08-27 1988-03-11 Mitsubishi Electric Corp Data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6356731A (en) * 1986-08-27 1988-03-11 Mitsubishi Electric Corp Data processor

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