JPS5697120A - Loading system of initial program - Google Patents

Loading system of initial program

Info

Publication number
JPS5697120A
JPS5697120A JP17217679A JP17217679A JPS5697120A JP S5697120 A JPS5697120 A JP S5697120A JP 17217679 A JP17217679 A JP 17217679A JP 17217679 A JP17217679 A JP 17217679A JP S5697120 A JPS5697120 A JP S5697120A
Authority
JP
Japan
Prior art keywords
flp
stored
disc
ram
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17217679A
Other languages
Japanese (ja)
Inventor
Shigeki Yanagida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17217679A priority Critical patent/JPS5697120A/en
Publication of JPS5697120A publication Critical patent/JPS5697120A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain the load system which can program the entire surface of one floppy disc without losing conventionality, by sufficiently using the firmware at a central processing unit.
CONSTITUTION: A bus BS is drawn from a central processing unit CPU incorporating the read only memory ROM where the firmware performing the function of the initial program loading is stored, and it is connected with RAM being the main memory unit and the floppy disc FLP via the input and output port FP. With this constitution, the disc FLP is stored with the load address, load length, start address, and system name such as record head address, and these parameter information is read out with the memory ROM when the power supply is applied for the loading, and the system name is stored in the working area WR of the memory unit RAM. Further, the parameter in the disc FLP is sequentially loaded to the memory unit RAM via the port FP not via the processor CPU.
COPYRIGHT: (C)1981,JPO&Japio
JP17217679A 1979-12-29 1979-12-29 Loading system of initial program Pending JPS5697120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17217679A JPS5697120A (en) 1979-12-29 1979-12-29 Loading system of initial program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17217679A JPS5697120A (en) 1979-12-29 1979-12-29 Loading system of initial program

Publications (1)

Publication Number Publication Date
JPS5697120A true JPS5697120A (en) 1981-08-05

Family

ID=15936976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17217679A Pending JPS5697120A (en) 1979-12-29 1979-12-29 Loading system of initial program

Country Status (1)

Country Link
JP (1) JPS5697120A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59116875A (en) * 1982-12-23 1984-07-05 Fujitsu Ltd Ipl method of multiprocessor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59116875A (en) * 1982-12-23 1984-07-05 Fujitsu Ltd Ipl method of multiprocessor system
JPH0430062B2 (en) * 1982-12-23 1992-05-20

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