JPS5696341A - Microprogram control data processing device - Google Patents

Microprogram control data processing device

Info

Publication number
JPS5696341A
JPS5696341A JP17220679A JP17220679A JPS5696341A JP S5696341 A JPS5696341 A JP S5696341A JP 17220679 A JP17220679 A JP 17220679A JP 17220679 A JP17220679 A JP 17220679A JP S5696341 A JPS5696341 A JP S5696341A
Authority
JP
Japan
Prior art keywords
instruction
error
decoder
micro instruction
end signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17220679A
Other languages
Japanese (ja)
Other versions
JPS593784B2 (en
Inventor
Kazuhiro Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54172206A priority Critical patent/JPS593784B2/en
Publication of JPS5696341A publication Critical patent/JPS5696341A/en
Publication of JPS593784B2 publication Critical patent/JPS593784B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To restrain the time delay due to error correction within 1t, by generating the end signal at the timing after decoding of the corrected micro instruction in the decoder when error display is performed.
CONSTITUTION: After the micro instruction read from control storage device 1 is set to instruction register 6 without error correction, the decoding processing of decoder 7 is started. If an error exists, presence or absence of the error is decided, and processing synchronizing part 10 delays generation of the micro instruction end signal by 1t and generates the decode end signal at the following timing. During this time, the corrected micro instruction is set to instruction register 6 and is decoded by decoder 7 to execute the micro instruction. By utilizing that 1t is required for setting the instruction from data register 3 to instruction register, the time delay due to error correction is restrained within it.
COPYRIGHT: (C)1981,JPO&Japio
JP54172206A 1979-12-28 1979-12-28 Microprogram control data processing device Expired JPS593784B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54172206A JPS593784B2 (en) 1979-12-28 1979-12-28 Microprogram control data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54172206A JPS593784B2 (en) 1979-12-28 1979-12-28 Microprogram control data processing device

Publications (2)

Publication Number Publication Date
JPS5696341A true JPS5696341A (en) 1981-08-04
JPS593784B2 JPS593784B2 (en) 1984-01-26

Family

ID=15937547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54172206A Expired JPS593784B2 (en) 1979-12-28 1979-12-28 Microprogram control data processing device

Country Status (1)

Country Link
JP (1) JPS593784B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214043A (en) * 1984-04-09 1985-10-26 Fujitsu Ltd Pipeline control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214043A (en) * 1984-04-09 1985-10-26 Fujitsu Ltd Pipeline control circuit

Also Published As

Publication number Publication date
JPS593784B2 (en) 1984-01-26

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