JPS5694885A - Charge transfer method - Google Patents

Charge transfer method

Info

Publication number
JPS5694885A
JPS5694885A JP17293979A JP17293979A JPS5694885A JP S5694885 A JPS5694885 A JP S5694885A JP 17293979 A JP17293979 A JP 17293979A JP 17293979 A JP17293979 A JP 17293979A JP S5694885 A JPS5694885 A JP S5694885A
Authority
JP
Japan
Prior art keywords
charge
pulse
capacity
transistor
shifted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17293979A
Other languages
Japanese (ja)
Inventor
Toru Takamura
Sumio Terakawa
Takahiro Yamada
Izumi Murozono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP17293979A priority Critical patent/JPS5694885A/en
Publication of JPS5694885A publication Critical patent/JPS5694885A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To increase vertical transfer efficiency in the charge transfer transfer system of a MOS-type solid state pickup device, by providing the 3rd capacity element having a bias charge injecting function to the 1st capacity element between the 1st and 2nd capacity elements. CONSTITUTION:The full charge of the photodiode 31 of cpacity CP is shifted onto the transmission line 35 of capacity CL larger than CP by the scan pulse sent from the vertical shift register 34 and through the MOS switch 32. The MOS transistor 36 conducts by the pulse VTG and at t1, and then the bias charge is injected to the vertical transmission line 35 from the drain part N. The potential of the part N increases with application of pulse VTC at t2, and then the two types of charge on the line 35 are shifted to the part N. The transistor 36 becomes nonconductive at t3 and by zero of the pulse VTG. The charge of the part N is shifted to the horizontal shift register 312 at t5 and by the shift pulse VTB. Thus the charge on the line 35 can be increased by the injection of the bias charge of the transistor 36. As a result, the vertical transfer efficiency is increased.
JP17293979A 1979-12-27 1979-12-27 Charge transfer method Pending JPS5694885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17293979A JPS5694885A (en) 1979-12-27 1979-12-27 Charge transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17293979A JPS5694885A (en) 1979-12-27 1979-12-27 Charge transfer method

Publications (1)

Publication Number Publication Date
JPS5694885A true JPS5694885A (en) 1981-07-31

Family

ID=15951143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17293979A Pending JPS5694885A (en) 1979-12-27 1979-12-27 Charge transfer method

Country Status (1)

Country Link
JP (1) JPS5694885A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6030151A (en) * 1983-07-28 1985-02-15 Nec Corp Designing method of wiring for integrated circuit
JPS6155784A (en) * 1984-08-28 1986-03-20 Toshiba Corp Histogram arithmetic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6030151A (en) * 1983-07-28 1985-02-15 Nec Corp Designing method of wiring for integrated circuit
JPS6155784A (en) * 1984-08-28 1986-03-20 Toshiba Corp Histogram arithmetic circuit

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