JPS5694782A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5694782A
JPS5694782A JP17185379A JP17185379A JPS5694782A JP S5694782 A JPS5694782 A JP S5694782A JP 17185379 A JP17185379 A JP 17185379A JP 17185379 A JP17185379 A JP 17185379A JP S5694782 A JPS5694782 A JP S5694782A
Authority
JP
Japan
Prior art keywords
area
channel
channel stopper
punch
monitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17185379A
Other languages
Japanese (ja)
Inventor
Shoji Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17185379A priority Critical patent/JPS5694782A/en
Publication of JPS5694782A publication Critical patent/JPS5694782A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To prevent an inversion layer from occurrence and to eliminate a channel leak current by a method wherein a channel stopper area is installed on a monitor. CONSTITUTION:A p type channel stopper area 11 of a high concentration is formed so as to surround an area 7 of a monitor 9. Since the channel stopper area 11 is a high concentration area, an inversion layer is not generated on a p type surface area. With this, even when a punch through voltage is measured, a channel leak current is not generated, as a result, the punch through voltage value can be measured, exactly.
JP17185379A 1979-12-28 1979-12-28 Semiconductor device Pending JPS5694782A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17185379A JPS5694782A (en) 1979-12-28 1979-12-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17185379A JPS5694782A (en) 1979-12-28 1979-12-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5694782A true JPS5694782A (en) 1981-07-31

Family

ID=15930983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17185379A Pending JPS5694782A (en) 1979-12-28 1979-12-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5694782A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081514A (en) * 1988-12-27 1992-01-14 Nec Corporation Protection circuit associated with input terminal of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081514A (en) * 1988-12-27 1992-01-14 Nec Corporation Protection circuit associated with input terminal of semiconductor device

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