JPS5694448A - Information processing device - Google Patents

Information processing device

Info

Publication number
JPS5694448A
JPS5694448A JP17069279A JP17069279A JPS5694448A JP S5694448 A JPS5694448 A JP S5694448A JP 17069279 A JP17069279 A JP 17069279A JP 17069279 A JP17069279 A JP 17069279A JP S5694448 A JPS5694448 A JP S5694448A
Authority
JP
Japan
Prior art keywords
shift
data
registers
terminal
multiplexers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17069279A
Other languages
Japanese (ja)
Inventor
Masaaki Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP17069279A priority Critical patent/JPS5694448A/en
Publication of JPS5694448A publication Critical patent/JPS5694448A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To prevent the time loss of register data in the test to shorten the operation time, by connecting the two-way shift bus, which can be operated by the select signal of the direction indication signal circuit, to plural registers where data can be read and written.
CONSTITUTION: Plural registers 21.1W21.i are provided which are cascaded shiftably and read and write data in response to shift indication, and multiplexers 24.1W 24.(i+1) are connected between inputs and outputs of these registers 21.1W21.i, thereby constituting two two-way shift busses to which data from the preceding stage as well as the succeeding stage can be input. Control terminal 13 is connected to multiplexers 24.1W24.(i+1) to supply the shift direction indicating signal, and the input terminal and output terminal 23 are connected to multiplexer 24.1 and multiplexer 24.(i+1) respectively. Then, the shift bus is selected by the shift direction indicating signal from terminal 13, and the time loss of register data in the test for registers 21.1W21.i is prevented to shorten the operation time.
COPYRIGHT: (C)1981,JPO&Japio
JP17069279A 1979-12-27 1979-12-27 Information processing device Pending JPS5694448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17069279A JPS5694448A (en) 1979-12-27 1979-12-27 Information processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17069279A JPS5694448A (en) 1979-12-27 1979-12-27 Information processing device

Publications (1)

Publication Number Publication Date
JPS5694448A true JPS5694448A (en) 1981-07-30

Family

ID=15909620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17069279A Pending JPS5694448A (en) 1979-12-27 1979-12-27 Information processing device

Country Status (1)

Country Link
JP (1) JPS5694448A (en)

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