JPS5786960A - Storage device - Google Patents

Storage device

Info

Publication number
JPS5786960A
JPS5786960A JP16380680A JP16380680A JPS5786960A JP S5786960 A JPS5786960 A JP S5786960A JP 16380680 A JP16380680 A JP 16380680A JP 16380680 A JP16380680 A JP 16380680A JP S5786960 A JPS5786960 A JP S5786960A
Authority
JP
Japan
Prior art keywords
input information
readout data
circuits
storage
readout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16380680A
Other languages
Japanese (ja)
Inventor
Toshihiko Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16380680A priority Critical patent/JPS5786960A/en
Publication of JPS5786960A publication Critical patent/JPS5786960A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To start the writing and reading operations of storage circuits simultaneously, and to process simultaneous requests to a different storage device instantaneously, by providing selecting circuits for input information and readout data corresponding to a storage circuit and an external circuit. CONSTITUTION:Through N units of input information selecting circuits WAS, M pieces of input information from M CPUs are selected with corresponding input information selection signals S and, when corresponding hold indication signals AD are supplied, held in N bank information registers WARs. Then, when a corresponding start signal E is supplied, write data in the input information held in the corresponding register WAR is written N storage circuits M' in write mode and readout data is outputted in readout mode. Then, N readout data from the storage circuits M' are selected by M readout data selecting circuit RS with corresponding readout data selection signals AR and then outputted to the M CPUs, so that simultaneous requests to different storage devices are processed instantaneously.
JP16380680A 1980-11-20 1980-11-20 Storage device Pending JPS5786960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16380680A JPS5786960A (en) 1980-11-20 1980-11-20 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16380680A JPS5786960A (en) 1980-11-20 1980-11-20 Storage device

Publications (1)

Publication Number Publication Date
JPS5786960A true JPS5786960A (en) 1982-05-31

Family

ID=15781053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16380680A Pending JPS5786960A (en) 1980-11-20 1980-11-20 Storage device

Country Status (1)

Country Link
JP (1) JPS5786960A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04153749A (en) * 1990-10-18 1992-05-27 Fujitsu Ltd Memory controller and storage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04153749A (en) * 1990-10-18 1992-05-27 Fujitsu Ltd Memory controller and storage

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