JPS5693177A - Static mos memory integrated circuit - Google Patents

Static mos memory integrated circuit

Info

Publication number
JPS5693177A
JPS5693177A JP16970979A JP16970979A JPS5693177A JP S5693177 A JPS5693177 A JP S5693177A JP 16970979 A JP16970979 A JP 16970979A JP 16970979 A JP16970979 A JP 16970979A JP S5693177 A JPS5693177 A JP S5693177A
Authority
JP
Japan
Prior art keywords
address
memory
group
circuits
action mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16970979A
Other languages
Japanese (ja)
Other versions
JPS6249675B2 (en
Inventor
Kazukiyo Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16970979A priority Critical patent/JPS5693177A/en
Publication of JPS5693177A publication Critical patent/JPS5693177A/en
Publication of JPS6249675B2 publication Critical patent/JPS6249675B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To obtain a high-speed static MOS memory IC having a small amount of consumption, by cutting the power supply to the memory in the wait mode and at the same time supplying the electric power only to the block of the divided address decoder groups in the action mode. CONSTITUTION:The prescribed bit part of the address signal supplied from the address inverter group 40 is turned into the selection signal to select the logic circuits 50-53 within the logic circuit group 300. Then the blocks 42-45 divided into the X decoder group 400 corresponding to the circuits 50-53 in the action mode of the memory by the AND process between the outputs of the circuits 50-53 plus the chip enable signal sent from the chip enable circuit 41 are selected. Furthermore the memory corresponding to the address given from the group 40 in the selected blocks is selected. As a result, the power supply is cut off in the nonaction and wait modes, and at the same time the power is supplied only to the selected address decoder block even in the action mode. Thus the useless power consumption can be avoided.
JP16970979A 1979-12-26 1979-12-26 Static mos memory integrated circuit Granted JPS5693177A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16970979A JPS5693177A (en) 1979-12-26 1979-12-26 Static mos memory integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16970979A JPS5693177A (en) 1979-12-26 1979-12-26 Static mos memory integrated circuit

Publications (2)

Publication Number Publication Date
JPS5693177A true JPS5693177A (en) 1981-07-28
JPS6249675B2 JPS6249675B2 (en) 1987-10-20

Family

ID=15891407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16970979A Granted JPS5693177A (en) 1979-12-26 1979-12-26 Static mos memory integrated circuit

Country Status (1)

Country Link
JP (1) JPS5693177A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0187289A2 (en) * 1984-12-31 1986-07-16 International Business Machines Corporation Hierarchical memory system
JP2007287331A (en) * 2007-08-09 2007-11-01 Renesas Technology Corp Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310229A (en) * 1976-07-16 1978-01-30 Mitsubishi Electric Corp Decoder circuit
JPS5484935A (en) * 1977-12-20 1979-07-06 Fujitsu Ltd Address selection circuit
JPS5668988A (en) * 1979-11-05 1981-06-09 Toshiba Corp Semiconductor memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310229A (en) * 1976-07-16 1978-01-30 Mitsubishi Electric Corp Decoder circuit
JPS5484935A (en) * 1977-12-20 1979-07-06 Fujitsu Ltd Address selection circuit
JPS5668988A (en) * 1979-11-05 1981-06-09 Toshiba Corp Semiconductor memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0187289A2 (en) * 1984-12-31 1986-07-16 International Business Machines Corporation Hierarchical memory system
JP2007287331A (en) * 2007-08-09 2007-11-01 Renesas Technology Corp Semiconductor device

Also Published As

Publication number Publication date
JPS6249675B2 (en) 1987-10-20

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