JPS6249675B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention is a static type device designed to reduce power consumption.
The present invention relates to MOS memory integrated circuits, particularly high-speed MOS memory integrated circuits using n-type MOS transistors.

Conventionally, this type of high-speed MOS memory integrated circuit has relatively high power consumption, so special care has been required in power distribution and thermal design for memory boards and memory systems in which a large number of MOS memory integrated circuits must be mounted.

One proposal for power reduction in this type of memory was published in the publication I.
SSC Digest of...
Technical Papers (ISSCC Digest cf
Richard Patsiley, published on pages 106 to 107 of Technical PaPers
Pashley et al.'s paper. In the static memory described in this paper, a transistor with a low gate threshold voltage is used as a power cutoff switch element in the X decoder and other peripheral circuits as shown in FIGURE 2.
It is inserted between Vcc and the circuit, and is controlled by the chip select signal CS. Chip select signal when the memory is in standby state
The CS causes the cutoff switch element to enter the cutoff state, cutting off power and reducing power consumption. When in the operating state, the cutoff switch element is in a conductive state and power is supplied to the circuit.

However, conventional static MOS memory integrated circuits, including the one proposed by Richard Patciley et al., can reduce power consumption during standby, but not during operation, and in particular waste power in address decoder circuits. The drawback was that the power consumption during operation of the memory, which was consumed and sped up, became significantly large.

An object of the present invention is to reduce power consumption during standby, and at the same time divide the X address decoder group and the Y address decoder group into a plurality of blocks so that only the blocks containing the selected X decoder and Y decoder are used. By supplying power, the power consumption of the X and Y decoders during operation is also reduced,
The object of the present invention is to provide a high-speed static type MOS integrated circuit with low power consumption.

According to the present invention, a chip select buffer circuit, an address buffer circuit, a logic circuit receiving an output signal of the chip select buffer circuit and an output signal of the address buffer circuit, and an address decoder circuit. and a MOS switch that is controlled by the output signal of the logic circuit and controls the power of the address decoder circuit.

Next, a specific example of the implementation of the present invention will be described with reference to the drawings, while comparing it with a conventional example.

FIG. 1 shows a schematic diagram of an address decoder group of a conventional static type MOS memory integrated circuit. The power of the X address decoder group 100 and the Y address decoder group 200 is controlled by the chip select buffer circuit 10. When a signal for selecting the chip in question is applied from the outside, the chip select buffer circuit 10 provides a high level output to the output line 11. At this time, the power control switches PCS1 to PCSN of the address decoders of the X address decoder group 100 become conductive, and the power supply line
Power is supplied from Vcc to the X address decoders XAD1-XADN. Similarly, power is also supplied to Y address decoder group 200. On the other hand, when the chip is not selected, that is, in a standby state, the chip select buffer circuit 10 provides a low level output to the output line 11. At this time, the power control switches PCS1 to PCSN are cut off, so the power to the X address decoder group 100 is cut off. Similarly, power to Y address decoder group 200 is also cut off. The symbols XAD1 to XADN in Figure 1 are NOR type decoders, which are usually the second
The circuit is as shown in the figure. In FIG. 2, the NOR decoder indicated by the symbol 2 in FIG. 1 is described as an example, but the same applies to other decoders. Load transistor RTN (usually a depletion type MOS transistor is used) and drive transistors DT1 to DTi (usually an enhancement type MOS transistor)
When the decoder is selected, the inputs A ₁ , A ₂ , ..., Ai are all low level, so the output W _N of the decoder is high. Indicates level voltage value. At this time, no current path occurs in the decoder, so no power is consumed. When no decoder is selected, inputs A ₁ , A ₂ , ...,
At least one of Ai becomes high level and at least one of the drive transistors DT1, DT2, ..., DTi becomes conductive, so the output W _N becomes low level and a current path from node P _N to ground occurs. , power is consumed. In a static MOS memory circuit, one decoder is selected in each of the X decoder group and the Y decoder group, and all remaining decoders are unselected and consume power. The faster the static MOS memory is, the greater the decoder capacity is, so the power consumed by the decoder group is also greater, and in some cases, the amount of power consumed is greater than that consumed by other circuits. Generally, high-speed static memories using n-channel MOS transistors have low power consumption during standby, but extremely high power consumption during operation, and the reason for this is the above-mentioned points.

FIG. 3 shows an embodiment of a static MOS memory integrated circuit according to the present invention. In this embodiment, the X decoder group (or Y decoder group)
Although the present invention is implemented only in 400, there is no problem in implementing the present invention in both the X and Y decoder groups at the same time, and the effect is doubled. Now, according to the present invention, the X decoder group 400 is divided into 2 ^k (k=1, 2, . . . , i) blocks. In this embodiment, k=2. The basic configuration of the X decoder group 400 itself is the same type of decoder group as the conventional decoder group 100 shown in FIG. One of the blocks 42, 43, 44, or 45 of the X decoder group 400 is controlled by the address signal output from the address inverter group 40.
A block is selected and a particular decoder within the block is selected. Logic circuit group 300 is NOR
It is made up of a circuit group and an AND circuit group. In this embodiment, four NOR circuits and four AND circuits are sufficient.
The logic circuits 50, 51, 52 are controlled by two specific bits of the address signal from the address inverter 40.
or 53 is selected, and the output of the selected logic circuit is ANDed with the output of the chip enable circuit 41 to produce an output signal. Therefore, when the output of the chip enable circuit 41 is at a low level, all the output signals of the logic circuit group 300 are at a low level, so that all the decoders in the X decoder group 400 are powered off. It becomes unselected. The number of logic circuits in logic circuit group 300 is the same as the number of divisions of X decoder group 400. Therefore, in this embodiment, one of the logic circuits 50, 51, 52, and 53 is selected by two specific bits, ANDed with the chip enable circuit 41, and outputs an output signal. Also, a specific block 4 of the X decoder group that receives the output signal from the logic circuit
Any block 2, 43, 44 or 45 may also be selected by two specific bits. By doing this, the X decoder group 4
Power is supplied only to the block selected by 2 bits of 00, and no power is supplied to other blocks. Therefore, if the number of decoders in one block is N, power is consumed by only N-1 decoders and one logic circuit. Address inverter circuit 40 and chip enable circuit 4
1 is the same as the conventional circuit, so it will not be discussed here. Considering only the power consumed by the decoder group, according to the conventional system, power is consumed by 4N-1 decoders. Now, as an example
Considering 4K bit RAM, N=16, so
Assuming that the power consumed by one decoder and one logic circuit is equal and one unit is used, the power consumed by the X decoder in the conventional system is 63 units, and in the system according to the present invention, the power consumed by the logic circuit group and the X decoder is 63 units. The power consumed considering both decoder groups is 16 units. It can be seen that the method according to the present invention can significantly reduce power consumption. X decoder group 40
An output of 0 is output by selecting one word line from one block of word line groups WG1, WG2, WG3, and WG4.

FIG. 4 shows an embodiment of a logic circuit that can be used in the embodiment of FIG. 88 is a power line. The signal from chip enable is at terminal 8.
4 is input. When the chip enable output is at a high level, the enhancement type MOS transistor 81 becomes conductive, so that a NOR circuit is formed between the depletion type MOS transistor 80 and the enhancement type MOS transistors 82 and 83. The specific 2-bit address signal is input to the terminals 85 and 87, and the 2-bit address signal is input to the terminal 86.
A bit NOR logic output is output. Power is supplied from a power line 87. When a low level signal is input to the terminal 84 as a signal from the chip enable, the enhancement type MOS transistor 8
Since 1 is cut off, a low level is output to terminal 86 regardless of the 2-bit address input. As can be seen from the above explanation, the circuit shown in FIG. 4 can perform the logic of NOR of the 2-bit address signal and AND of the chip enable output.

FIG. 5 shows another embodiment of a logic circuit that can be employed in the present invention. A chip enable output is applied to terminal 500. The chip enable output is
The inverted signal is input to an inverter circuit made up of MOS transistors 91 and 92.
The signal is input to a NOR circuit made up of transistors 96, 93, 94, and 95, and output from an output terminal 503. A 2-bit address signal is applied to terminals 501 and 502. Note that power is supplied from a power line 98. This circuit can perform the same logic as the logic circuit of FIG.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an address decoder group of a conventional static type MOS memory integrated circuit.
100 is an X decoder group, and 200 is a Y decoder group. Vcc is the power line, 10 is the chip select buffer circuit, 11 is the output line, PCS1,...
..., PCSN is the power control switch, XAD1, ...,
XADN is the X address decoder, W ₁ , ..., W _N
is the X decoder output, P ₁ , ..., P _N is the node, Y ₁ ,
..., Y _N is the Y address decoder output.
Figure 2 shows the X address decoder XAD in Figure 1.
1,..., typical used as XADN
This is a NOR type decoder circuit. Figure 3 shows a static MOS memory integrated circuit according to the present invention.
4 is a block diagram of a decoder group and a logic circuit group;
0 is an address inverter group, 41 is a chip enable circuit, 300 is a logic circuit group, and 400 is an X decoder group. W _G1 , W _G2 ,
W _G3 and W _G4 are word lines. FIG. 4 shows one embodiment of the logic circuit 300 of FIG. 3, and FIG. 5 shows another embodiment. 88 and 98 are power supply lines, 84 and 500 are terminals for applying chip enable output,
85, 87, 501, 502 are application terminals for 2-bit address signals, and 86 and 503 are output terminals.

Claims (1)

[Claims] 1 A chip select buffer circuit, an address buffer circuit, an address decoder circuit, and an output signal of the chip select buffer circuit and an output signal of the address buffer circuit as inputs, and a selected circuit of the address decoder circuit. 1. A static MOS memory integrated circuit, comprising: a logic circuit that outputs a control signal to supply power only to the selected blocks.