JPS5690626A - Driving circuit with latch function - Google Patents

Driving circuit with latch function

Info

Publication number
JPS5690626A
JPS5690626A JP16879679A JP16879679A JPS5690626A JP S5690626 A JPS5690626 A JP S5690626A JP 16879679 A JP16879679 A JP 16879679A JP 16879679 A JP16879679 A JP 16879679A JP S5690626 A JPS5690626 A JP S5690626A
Authority
JP
Japan
Prior art keywords
output terminal
gate output
load capacity
gate
capacity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16879679A
Other languages
Japanese (ja)
Inventor
Norimasa Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16879679A priority Critical patent/JPS5690626A/en
Publication of JPS5690626A publication Critical patent/JPS5690626A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET

Abstract

PURPOSE:To retain information securely by discharging a load capacity to the earth level when a reset pulse is applied. CONSTITUTION:As a reset pulse which is never superposed upon a clock signal is inputted, floating capacity Cs and load capacity CL are discharged to the earth level via FETs Q2 and Q6 and outputs of gate output terminal A and driving output terminal B are held at the earth level. Next, as a set pulse is inputted, FETQ1 charges only floating capacity Cs since FETQ5 is off, and gate output terminal A is held at the power level by the charging. At this time, channel capacitor C1 is formed, and when a clock signal is applied, the potential of gate output terminal A rises through the coupling of the capacitor. Since FETQ5 stays cut off, load capacity CL is isolated from gate output terminal A and the potential of gate output terminal A rises securely to drive the gate of driving FETQ3 strongly, charging load capacity CL rapidly to the power level.
JP16879679A 1979-12-24 1979-12-24 Driving circuit with latch function Pending JPS5690626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16879679A JPS5690626A (en) 1979-12-24 1979-12-24 Driving circuit with latch function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16879679A JPS5690626A (en) 1979-12-24 1979-12-24 Driving circuit with latch function

Publications (1)

Publication Number Publication Date
JPS5690626A true JPS5690626A (en) 1981-07-22

Family

ID=15874626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16879679A Pending JPS5690626A (en) 1979-12-24 1979-12-24 Driving circuit with latch function

Country Status (1)

Country Link
JP (1) JPS5690626A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989005547A1 (en) * 1987-12-01 1989-06-15 International Business Machines Corporation A multi-emitter bicmos logic circuit family with superior performance
US5113087A (en) * 1988-07-22 1992-05-12 Kabushiki Kaisha Toshiba Output circuit
JP2013168944A (en) * 2013-02-22 2013-08-29 Semiconductor Energy Lab Co Ltd Semiconductor device, display device, and electronic apparatus
US8841680B2 (en) 2001-08-10 2014-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2014222892A (en) * 2014-06-18 2014-11-27 株式会社半導体エネルギー研究所 Semiconductor device, display device, and electronic apparatus
JP2015144459A (en) * 2015-03-04 2015-08-06 株式会社半導体エネルギー研究所 Semiconductor device and display device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989005547A1 (en) * 1987-12-01 1989-06-15 International Business Machines Corporation A multi-emitter bicmos logic circuit family with superior performance
US5113087A (en) * 1988-07-22 1992-05-12 Kabushiki Kaisha Toshiba Output circuit
US8841680B2 (en) 2001-08-10 2014-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9343485B2 (en) 2001-08-10 2016-05-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9601525B2 (en) 2001-08-10 2017-03-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9893094B2 (en) 2001-08-10 2018-02-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2013168944A (en) * 2013-02-22 2013-08-29 Semiconductor Energy Lab Co Ltd Semiconductor device, display device, and electronic apparatus
JP2014222892A (en) * 2014-06-18 2014-11-27 株式会社半導体エネルギー研究所 Semiconductor device, display device, and electronic apparatus
JP2015144459A (en) * 2015-03-04 2015-08-06 株式会社半導体エネルギー研究所 Semiconductor device and display device

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