JPS5687137A - Printing system of electronic register - Google Patents

Printing system of electronic register

Info

Publication number
JPS5687137A
JPS5687137A JP16444079A JP16444079A JPS5687137A JP S5687137 A JPS5687137 A JP S5687137A JP 16444079 A JP16444079 A JP 16444079A JP 16444079 A JP16444079 A JP 16444079A JP S5687137 A JPS5687137 A JP S5687137A
Authority
JP
Japan
Prior art keywords
data
printing
cpu7
memory
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16444079A
Other languages
Japanese (ja)
Other versions
JPS6239467B2 (en
Inventor
Hanzo Tsuzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP16444079A priority Critical patent/JPS5687137A/en
Publication of JPS5687137A publication Critical patent/JPS5687137A/en
Publication of JPS6239467B2 publication Critical patent/JPS6239467B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To facilitate an easy detection of the printed data and increase the efficiency of the totalizing work, by deciding various mode states and printing the section data different according to the mode state before or after printing of the data in the decided mode state.
CONSTITUTION: The input control circuit 2 connected to the input part 1, the display control circuit 4 connected to the display part 3 and the print control circuit 6 connected to the printing part 5 are connected to the electronic register CPU7 via the data bus DB. These control circuits 2, 4 and 6 supply the control signals CSIW CSIII from the CPU7 and carry out the receiving of the data based on the designation of the signals CSIWCSIII. At the same time, the totalizing memory 8 is connected to the CPU7 via the address bus AB. The output of the memory 8 is delivered to the bus DB. Then various mode states are decided at the CPU7, and the printing is carried out for the section data before or after printing of the data under the control of the circuit 2. Thus the totalization can be facilitated for the data of the memory 8.
COPYRIGHT: (C)1981,JPO&Japio
JP16444079A 1979-12-17 1979-12-17 Printing system of electronic register Granted JPS5687137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16444079A JPS5687137A (en) 1979-12-17 1979-12-17 Printing system of electronic register

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16444079A JPS5687137A (en) 1979-12-17 1979-12-17 Printing system of electronic register

Publications (2)

Publication Number Publication Date
JPS5687137A true JPS5687137A (en) 1981-07-15
JPS6239467B2 JPS6239467B2 (en) 1987-08-24

Family

ID=15793197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16444079A Granted JPS5687137A (en) 1979-12-17 1979-12-17 Printing system of electronic register

Country Status (1)

Country Link
JP (1) JPS5687137A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155988A (en) * 1982-03-11 1983-09-16 Ishida Scales Mfg Co Ltd Label printing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155988A (en) * 1982-03-11 1983-09-16 Ishida Scales Mfg Co Ltd Label printing system

Also Published As

Publication number Publication date
JPS6239467B2 (en) 1987-08-24

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