JPS5685946A - Time sharing multiplex transmission control system - Google Patents

Time sharing multiplex transmission control system

Info

Publication number
JPS5685946A
JPS5685946A JP16308779A JP16308779A JPS5685946A JP S5685946 A JPS5685946 A JP S5685946A JP 16308779 A JP16308779 A JP 16308779A JP 16308779 A JP16308779 A JP 16308779A JP S5685946 A JPS5685946 A JP S5685946A
Authority
JP
Japan
Prior art keywords
signal
output
clock
gate
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16308779A
Other languages
Japanese (ja)
Inventor
Motoharu Terada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP16308779A priority Critical patent/JPS5685946A/en
Publication of JPS5685946A publication Critical patent/JPS5685946A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To make it possible to automatically detect a variation of the self-oscillation frequency, by counting a clock from the self-oscillator for generating a signal processing clock signal, provided on each terminal, by the counter which operates in the return holding pulse period. CONSTITUTION:The clock output F of the self-oscillating circuit 5 is provided to the logical circuit L, and also it is provided to the counter CT through the gate G1 which is opened by an address coincidence signal C. The output of the CT is connected to the A terminals of the comparators CP1, CP2, and the B terminals of CP1 and CP2 and connected to the upper limit setting swtich S1 and the lower limit setting switch S2, respectively. CP1 and CP2 input the output signals to the data terminal D of the FF through the gate G2, in case of B>A by comparing the set point of the switch S1 with the output of the CT, and in case of B<A by comparing the set point of the switch S2 with the output of the CT, respectively. The signal which has passed through the gate G3 of two inputs of the signal C and the transmission input signal A is input to the clock terminal CL of the FF, and when the signal F has exceeded the set point range, the FF outputs a frequency variation detecting signal H.
JP16308779A 1979-12-15 1979-12-15 Time sharing multiplex transmission control system Pending JPS5685946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16308779A JPS5685946A (en) 1979-12-15 1979-12-15 Time sharing multiplex transmission control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16308779A JPS5685946A (en) 1979-12-15 1979-12-15 Time sharing multiplex transmission control system

Publications (1)

Publication Number Publication Date
JPS5685946A true JPS5685946A (en) 1981-07-13

Family

ID=15766930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16308779A Pending JPS5685946A (en) 1979-12-15 1979-12-15 Time sharing multiplex transmission control system

Country Status (1)

Country Link
JP (1) JPS5685946A (en)

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