JPS5685152A - Display buffer control system - Google Patents

Display buffer control system

Info

Publication number
JPS5685152A
JPS5685152A JP16186379A JP16186379A JPS5685152A JP S5685152 A JPS5685152 A JP S5685152A JP 16186379 A JP16186379 A JP 16186379A JP 16186379 A JP16186379 A JP 16186379A JP S5685152 A JPS5685152 A JP S5685152A
Authority
JP
Japan
Prior art keywords
display
buffer
bus
common bus
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16186379A
Other languages
Japanese (ja)
Other versions
JPS6213688B2 (en
Inventor
Taiji Nosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16186379A priority Critical patent/JPS5685152A/en
Publication of JPS5685152A publication Critical patent/JPS5685152A/en
Publication of JPS6213688B2 publication Critical patent/JPS6213688B2/ja
Granted legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To avoid the waiting for vacancy of the main memory and thus increase the overall working efficiency of the control system, by installing a display exclusive buffer which is not connected to the common bus.
CONSTITUTION: The signals of the address 1, data bus 2 and control bus 3 are received at the common bus transmission/reception circuit 4, and a comparison is given to these signals at the comparator 5 whether they mean the address of the display buffer 9 in the main memory. If these signals are within the address range, the exclusive memory control circuit 7 is actuated to write the same data as the buffer 9 into the display exclusive buffer 10 through the data bus 2. In this case, the reading circuit 12 has to wait until the end of writing. Thus no common bus nor the main memory are used for the reading for display refresh. Accordingly, the display buffer can be read and written directly via the processor. In addition, the using efficiency is never lowered for the common bus regardless of the reading of the display unit.
COPYRIGHT: (C)1981,JPO&Japio
JP16186379A 1979-12-13 1979-12-13 Display buffer control system Granted JPS5685152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16186379A JPS5685152A (en) 1979-12-13 1979-12-13 Display buffer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16186379A JPS5685152A (en) 1979-12-13 1979-12-13 Display buffer control system

Publications (2)

Publication Number Publication Date
JPS5685152A true JPS5685152A (en) 1981-07-11
JPS6213688B2 JPS6213688B2 (en) 1987-03-28

Family

ID=15743385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16186379A Granted JPS5685152A (en) 1979-12-13 1979-12-13 Display buffer control system

Country Status (1)

Country Link
JP (1) JPS5685152A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5933542A (en) * 1982-08-18 1984-02-23 Nec Corp Display device
JPS60117327A (en) * 1983-11-30 1985-06-24 Fuji Xerox Co Ltd Display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5933542A (en) * 1982-08-18 1984-02-23 Nec Corp Display device
JPS60117327A (en) * 1983-11-30 1985-06-24 Fuji Xerox Co Ltd Display device

Also Published As

Publication number Publication date
JPS6213688B2 (en) 1987-03-28

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