JPS5676832A - Misinput preventing system - Google Patents

Misinput preventing system

Info

Publication number
JPS5676832A
JPS5676832A JP14056080A JP14056080A JPS5676832A JP S5676832 A JPS5676832 A JP S5676832A JP 14056080 A JP14056080 A JP 14056080A JP 14056080 A JP14056080 A JP 14056080A JP S5676832 A JPS5676832 A JP S5676832A
Authority
JP
Japan
Prior art keywords
output
circuits
input
17aw17d
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14056080A
Other languages
Japanese (ja)
Other versions
JPS5729736B2 (en
Inventor
Masayuki Hakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP14056080A priority Critical patent/JPS5676832A/en
Publication of JPS5676832A publication Critical patent/JPS5676832A/en
Publication of JPS5729736B2 publication Critical patent/JPS5729736B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Calculators And Similar Devices (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To secure an assured input to the computer, typewriter or the like, by preventing the chattering when the key is operated by inhibiting immediately the output of the key scan signal when the arithmetic action is started by the operation of keys.
CONSTITUTION: The information input keys 141W1416 are provided to the matrix circuit 11 comprising the row lines 121W124 plus the column lines 131W134 each. Then the row lines 121W124 are connected to the output terminals S1WS4 of the decoder 15. At the same time, the column lines 131W134 are added to one input of the AND circuits 17aW17d each, and the output of the OR circuit 18 is supplied to the circuits 17aW17d each via the FF19 and the like. Then the outputs of the circuits 17aW17d are stored into the registers 161W165 via the OR circuits 26aW26c, and the outputs of the egisters 161W165 are stored into the memory part 29 via the address decoder 28. The output of the address part 31 at the part 29 is applied to the registers 161W165 for addition, and the output of the decoder 15 is applied to the lines 121W124 in accordance with the count value of the above addition. Thus the chattering can be prevented when the key is operated and thus an assured input is possible.
COPYRIGHT: (C)1981,JPO&Japio
JP14056080A 1980-10-09 1980-10-09 Misinput preventing system Granted JPS5676832A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14056080A JPS5676832A (en) 1980-10-09 1980-10-09 Misinput preventing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14056080A JPS5676832A (en) 1980-10-09 1980-10-09 Misinput preventing system

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP11415273A Division JPS5727490B2 (en) 1973-10-11 1973-10-11

Publications (2)

Publication Number Publication Date
JPS5676832A true JPS5676832A (en) 1981-06-24
JPS5729736B2 JPS5729736B2 (en) 1982-06-24

Family

ID=15271512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14056080A Granted JPS5676832A (en) 1980-10-09 1980-10-09 Misinput preventing system

Country Status (1)

Country Link
JP (1) JPS5676832A (en)

Also Published As

Publication number Publication date
JPS5729736B2 (en) 1982-06-24

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