JPS5474328A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5474328A
JPS5474328A JP14173377A JP14173377A JPS5474328A JP S5474328 A JPS5474328 A JP S5474328A JP 14173377 A JP14173377 A JP 14173377A JP 14173377 A JP14173377 A JP 14173377A JP S5474328 A JPS5474328 A JP S5474328A
Authority
JP
Japan
Prior art keywords
line
bus
data processor
format
memory rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14173377A
Other languages
Japanese (ja)
Inventor
Katsumi Nishimura
Kuniaki Makabe
Yoshinori Morita
Hitoshi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14173377A priority Critical patent/JPS5474328A/en
Publication of JPS5474328A publication Critical patent/JPS5474328A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make the format of output logic free by assignging the output logic format of a key input part connected to a bus, on a data processor of a microcomputer equipped with a keyboard. CONSTITUTION:The device composed of jumper line JP and tri-state buffer TBF is connected to one-bit line l from the output of memory ROM of the microcomputer consisting of data processing part CPU, and input port INP, keybord KB, decoder DEC, memory ROM, and buffer BUF connected via address bus AB and data bus DB; and then, the bit of line l is assigned to this jumper line JP.
JP14173377A 1977-11-26 1977-11-26 Data processor Pending JPS5474328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14173377A JPS5474328A (en) 1977-11-26 1977-11-26 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14173377A JPS5474328A (en) 1977-11-26 1977-11-26 Data processor

Publications (1)

Publication Number Publication Date
JPS5474328A true JPS5474328A (en) 1979-06-14

Family

ID=15298935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14173377A Pending JPS5474328A (en) 1977-11-26 1977-11-26 Data processor

Country Status (1)

Country Link
JP (1) JPS5474328A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5659334A (en) * 1979-10-19 1981-05-22 Hitachi Ltd Device discrimination system
JPS6146637U (en) * 1984-08-31 1986-03-28 パイオニア株式会社 Mode programming circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131046A (en) * 1973-03-30 1974-12-16
JPS5210039A (en) * 1975-07-14 1977-01-26 Seikosha Co Ltd Supplemental controller of data processer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131046A (en) * 1973-03-30 1974-12-16
JPS5210039A (en) * 1975-07-14 1977-01-26 Seikosha Co Ltd Supplemental controller of data processer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5659334A (en) * 1979-10-19 1981-05-22 Hitachi Ltd Device discrimination system
JPS6146637U (en) * 1984-08-31 1986-03-28 パイオニア株式会社 Mode programming circuit
JPH049640Y2 (en) * 1984-08-31 1992-03-10

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