JPS5674730A - Input unit read system - Google Patents

Input unit read system

Info

Publication number
JPS5674730A
JPS5674730A JP15072479A JP15072479A JPS5674730A JP S5674730 A JPS5674730 A JP S5674730A JP 15072479 A JP15072479 A JP 15072479A JP 15072479 A JP15072479 A JP 15072479A JP S5674730 A JPS5674730 A JP S5674730A
Authority
JP
Japan
Prior art keywords
processing
data
cpu
transferred
central operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15072479A
Other languages
Japanese (ja)
Inventor
Sadao Iwakura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP15072479A priority Critical patent/JPS5674730A/en
Publication of JPS5674730A publication Critical patent/JPS5674730A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent a transfer error and take up the halt of the data transfer processing, by interrupting a specific input corresponding to the work which executes the processing of the central operation unit, in the electronic apparatus having the input unit and the central operation processing unit.
CONSTITUTION: When a data is transferred between the central operation processing unit CPU and the peripheral magnetic memory MM, CPU sets the latch FF1, inhibits the interruption request from the key matrix KM and the peripheral equipment PE, and prevents the fact that the processing for transferring a data is halted and a data transfer error occurs. In case when a data is transferred, a flag which is varied by depressing the break key BK is discriminated, and if the flag remains standing by interruption from the break key BK, the interruption request is transferred to CPU. As a result, CPU halts the data transfer from the memory MM, resets the latch FF1, makes it possible to interrupt from the matrix KM and the equipment PE, and ends the processing.
COPYRIGHT: (C)1981,JPO&Japio
JP15072479A 1979-11-22 1979-11-22 Input unit read system Pending JPS5674730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15072479A JPS5674730A (en) 1979-11-22 1979-11-22 Input unit read system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15072479A JPS5674730A (en) 1979-11-22 1979-11-22 Input unit read system

Publications (1)

Publication Number Publication Date
JPS5674730A true JPS5674730A (en) 1981-06-20

Family

ID=15503015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15072479A Pending JPS5674730A (en) 1979-11-22 1979-11-22 Input unit read system

Country Status (1)

Country Link
JP (1) JPS5674730A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224831A (en) * 1986-03-25 1987-10-02 Nec Corp Data reception processing system
JPS63197285A (en) * 1986-12-22 1988-08-16 ゼネラル・エレクトリック・カンパニイ Hybrid type interrupt processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224831A (en) * 1986-03-25 1987-10-02 Nec Corp Data reception processing system
JPS63197285A (en) * 1986-12-22 1988-08-16 ゼネラル・エレクトリック・カンパニイ Hybrid type interrupt processor

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