JPS567453A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS567453A
JPS567453A JP8136579A JP8136579A JPS567453A JP S567453 A JPS567453 A JP S567453A JP 8136579 A JP8136579 A JP 8136579A JP 8136579 A JP8136579 A JP 8136579A JP S567453 A JPS567453 A JP S567453A
Authority
JP
Japan
Prior art keywords
sealing
chip
glass layer
airtight
returned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8136579A
Other languages
Japanese (ja)
Inventor
Tatsumi Shirasu
Tatsu Ito
Shuji Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8136579A priority Critical patent/JPS567453A/en
Publication of JPS567453A publication Critical patent/JPS567453A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To ensure sufficient sealing allowance and prevent faulty airtight by a method wherein a device is reheated in an atmosphere with pressure relatively higher than the case of sealing after the device is sealed, and sealing gas extruded to the outside is returned to the inside. CONSTITUTION:A lead 12 is fastened onto the circumference with an adhesive layer 11 of glass with the low melting point while surrounding a concave portion at the center of a ceramic base 10. An IC chip 14 is fast stuck into the concave portion, a wire is connected, and the surface of the chip is coated with polyimide resin 16 for shielding alpha-rays. A conver 18 in ceramics is stacked onto the base 10 through a glass layer 17 with the low melting point, welded and sealed. The resin 16 is decomposed at a temperature of heat treatment at that time and gas pressure increases, the glass layer 17 is extruded, and sealing allowance is decreased. The chip is thermally treated in an atmosphere at gas pressure higher than a sealing process, and the glass layer is remelted and returned to the inside. Thus, the generation of faulty airtight is sharply reduced, and the reliability of a device is improved.
JP8136579A 1979-06-29 1979-06-29 Manufacture of semiconductor device Pending JPS567453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8136579A JPS567453A (en) 1979-06-29 1979-06-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8136579A JPS567453A (en) 1979-06-29 1979-06-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS567453A true JPS567453A (en) 1981-01-26

Family

ID=13744293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8136579A Pending JPS567453A (en) 1979-06-29 1979-06-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS567453A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991007776A1 (en) * 1989-11-15 1991-05-30 Olin Corporation A method for housing a tape-bonded electronic device and the package employed
EP1333489A3 (en) * 2002-01-31 2006-07-26 Fujitsu Hitachi Plasma Display Limited Semiconductor chip with a protective film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991007776A1 (en) * 1989-11-15 1991-05-30 Olin Corporation A method for housing a tape-bonded electronic device and the package employed
US5073521A (en) * 1989-11-15 1991-12-17 Olin Corporation Method for housing a tape-bonded electronic device and the package employed
EP1333489A3 (en) * 2002-01-31 2006-07-26 Fujitsu Hitachi Plasma Display Limited Semiconductor chip with a protective film
US7224044B2 (en) 2002-01-31 2007-05-29 Fujitsu Hitachi Plasma Display Limited Semiconductor chip mounting substrate and flat display

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