JPS5669932A - Logic circuit - Google Patents
Logic circuitInfo
- Publication number
- JPS5669932A JPS5669932A JP14667679A JP14667679A JPS5669932A JP S5669932 A JPS5669932 A JP S5669932A JP 14667679 A JP14667679 A JP 14667679A JP 14667679 A JP14667679 A JP 14667679A JP S5669932 A JPS5669932 A JP S5669932A
- Authority
- JP
- Japan
- Prior art keywords
- level
- output out
- trq4
- electric power
- change
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Pulse Circuits (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To make it possible to obtain a stable time lag only in fall with small electric power consumtion and a small number of elements, by detecting the output change of an electric power switching type logic circuit, and by delaying only a change at the fall by controlling the current level. CONSTITUTION:When input voltage VIN is at a low level, output OUT' is at a high level and the level applied to TRQ4 connected via transistor TRQ6 constituting an emitter follower also increases, so that TRQ3 and TRQ4 will turn off and on respectively. Next, as voltage VIN rises in level gradually, output OUT' falls in level and output OUT rises to flow electric current through TRQ1 while the current flowing through TRQ2 is reduced. The electric current having flowed to TRQ4 is shunt to TRQ3 and the total current flowing to TRs Q1 and Q2 is reduced, so that although output OUT rises in level, it will take a long time for output OUT to change to the low level. Consequently, a stable time lag only in rise can be obtained with small electric power consumption and a small number of elements.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14667679A JPS5669932A (en) | 1979-11-13 | 1979-11-13 | Logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14667679A JPS5669932A (en) | 1979-11-13 | 1979-11-13 | Logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5669932A true JPS5669932A (en) | 1981-06-11 |
Family
ID=15413072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14667679A Pending JPS5669932A (en) | 1979-11-13 | 1979-11-13 | Logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5669932A (en) |
-
1979
- 1979-11-13 JP JP14667679A patent/JPS5669932A/en active Pending
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