JPS566539A - Signal level converting circuit - Google Patents

Signal level converting circuit

Info

Publication number
JPS566539A
JPS566539A JP8135079A JP8135079A JPS566539A JP S566539 A JPS566539 A JP S566539A JP 8135079 A JP8135079 A JP 8135079A JP 8135079 A JP8135079 A JP 8135079A JP S566539 A JPS566539 A JP S566539A
Authority
JP
Japan
Prior art keywords
circuit
signal level
level converting
fluctuation
converting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8135079A
Other languages
Japanese (ja)
Other versions
JPH0158696B2 (en
Inventor
Nobuaki Kitamura
Koji Masuda
Masao Mizukami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP8135079A priority Critical patent/JPS566539A/en
Priority to US06/157,936 priority patent/US4366397A/en
Priority to DE19803024273 priority patent/DE3024273A1/en
Publication of JPS566539A publication Critical patent/JPS566539A/en
Publication of JPH0158696B2 publication Critical patent/JPH0158696B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01812—Interface arrangements with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a signal level converting circuit which is capable of a high- speed switching and has the increased power voltage fluctuation working range, by making the current value of current source transistor TR depend on the difference between the positive and negative power voltages. CONSTITUTION:N-MOS memory l3 is driven by emitter-coupled logic circuit l1 via level converting circuit l2. Bias circuit 2 within circuit l2 is connected to positive and negative power voltages VCC and VEE to be driven by the voltage difference. Thus the current flowing to power source TRQ10 is not fluctuated so large as conventional even with the fluctuation of VCC and VEE. As a result, the fluctuation is reduced for current I0 at circuit l2, and thus the potential at joint N1 has no big variation. Accordingly, the signal level at output terminal P14 can be kept steady to N-MOS memory l3.
JP8135079A 1979-06-29 1979-06-29 Signal level converting circuit Granted JPS566539A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP8135079A JPS566539A (en) 1979-06-29 1979-06-29 Signal level converting circuit
US06/157,936 US4366397A (en) 1979-06-29 1980-06-09 Level conversion circuit
DE19803024273 DE3024273A1 (en) 1979-06-29 1980-06-27 LEVEL CONVERTER CONTROL

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8135079A JPS566539A (en) 1979-06-29 1979-06-29 Signal level converting circuit

Publications (2)

Publication Number Publication Date
JPS566539A true JPS566539A (en) 1981-01-23
JPH0158696B2 JPH0158696B2 (en) 1989-12-13

Family

ID=13743910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8135079A Granted JPS566539A (en) 1979-06-29 1979-06-29 Signal level converting circuit

Country Status (1)

Country Link
JP (1) JPS566539A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58213521A (en) * 1982-05-26 1983-12-12 レイセオン　カンパニ− Comparator circuit
EP0404360A2 (en) * 1989-06-20 1990-12-27 Advanced Micro Devices, Inc. Shielded transistor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5369561A (en) * 1976-12-02 1978-06-21 Fujitsu Ltd Level converting circuit
JPS5478654A (en) * 1977-12-05 1979-06-22 Nec Corp Current switch type logic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5369561A (en) * 1976-12-02 1978-06-21 Fujitsu Ltd Level converting circuit
JPS5478654A (en) * 1977-12-05 1979-06-22 Nec Corp Current switch type logic circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58213521A (en) * 1982-05-26 1983-12-12 レイセオン　カンパニ− Comparator circuit
JPH0452654B2 (en) * 1982-05-26 1992-08-24 Raytheon Co
EP0404360A2 (en) * 1989-06-20 1990-12-27 Advanced Micro Devices, Inc. Shielded transistor device

Also Published As

Publication number Publication date
JPH0158696B2 (en) 1989-12-13

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