JPS5662494A - Switching control system for information transfer path - Google Patents

Switching control system for information transfer path

Info

Publication number
JPS5662494A
JPS5662494A JP13834679A JP13834679A JPS5662494A JP S5662494 A JPS5662494 A JP S5662494A JP 13834679 A JP13834679 A JP 13834679A JP 13834679 A JP13834679 A JP 13834679A JP S5662494 A JPS5662494 A JP S5662494A
Authority
JP
Japan
Prior art keywords
information
input
common processor
signal
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13834679A
Other languages
Japanese (ja)
Other versions
JPS5917597B2 (en
Inventor
Kazuo Yamagiwa
Tadashi Mizuno
Tadao Ooka
Hiroshi Manba
Yasuo Kato
Tomoyasu Mishima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP13834679A priority Critical patent/JPS5917597B2/en
Publication of JPS5662494A publication Critical patent/JPS5662494A/en
Publication of JPS5917597B2 publication Critical patent/JPS5917597B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54558—Redundancy, stand-by

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To form the system with much redundancy, by inputting the switching designating information with the operation waiting status information and the instruction of common processor, to the information transfer path switching device. CONSTITUTION:When a common processor CC0 is in operating state, the information transfer path switching device SW connects the input and output control device IOC0 and the input and output device IO when the operation waiting status information ACT0 has a signal and the information ACT1 has not signal, and the common processor CC0 performs information transfer. In this case, if the input and output control device IOC0 has a failure, the program processed at the common processor CC0 executes the instruction outputting the relay operating signal, starts the bus control device SBC0 and transmits the command information. The switching device SW connects the input and output control device IOC1 and the input and output device IO with the signal from the relay drive circuit RD and the common processor CC0 starts the transfer of information.
JP13834679A 1979-10-26 1979-10-26 Information transfer path switching control method Expired JPS5917597B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13834679A JPS5917597B2 (en) 1979-10-26 1979-10-26 Information transfer path switching control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13834679A JPS5917597B2 (en) 1979-10-26 1979-10-26 Information transfer path switching control method

Publications (2)

Publication Number Publication Date
JPS5662494A true JPS5662494A (en) 1981-05-28
JPS5917597B2 JPS5917597B2 (en) 1984-04-21

Family

ID=15219767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13834679A Expired JPS5917597B2 (en) 1979-10-26 1979-10-26 Information transfer path switching control method

Country Status (1)

Country Link
JP (1) JPS5917597B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166294A (en) * 1984-12-27 1986-07-26 Fujitsu Ltd Common control system of input and output device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166294A (en) * 1984-12-27 1986-07-26 Fujitsu Ltd Common control system of input and output device
JPH0418757B2 (en) * 1984-12-27 1992-03-27 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS5917597B2 (en) 1984-04-21

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