JPS5649516A - Semiconductor wafer - Google Patents

Semiconductor wafer

Info

Publication number
JPS5649516A
JPS5649516A JP12496079A JP12496079A JPS5649516A JP S5649516 A JPS5649516 A JP S5649516A JP 12496079 A JP12496079 A JP 12496079A JP 12496079 A JP12496079 A JP 12496079A JP S5649516 A JPS5649516 A JP S5649516A
Authority
JP
Japan
Prior art keywords
targets
region
wafer
semiconductor wafer
surrounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12496079A
Other languages
Japanese (ja)
Inventor
Seiichi Nakamura
Teruo Iino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12496079A priority Critical patent/JPS5649516A/en
Publication of JPS5649516A publication Critical patent/JPS5649516A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To elevate the positioning accuracy of a semiconductor wafer by a method wherein at least at two places on the surface of a semiconductor substrate providing with a metal wiring and a scribing region, etc., targets consisting of an uneven region being made of a dielectric layer and a plane region being surrounded with the uneven region are provided. CONSTITUTION:A semiconductor wafer 2 is put on a table 1, a laser beam generating from a laser source is projected to it through reflecting mirrors 5, 5', the reflected laser beam is condensed by a lens 6 and is applied to a receiving part to probe the wafer 2. In this constitution, to make the position of a metal wiring, etc., being provided on the wafer 1 to be definite, targets are formed on the wafer 1 fixing the position. At this time, targets are made as follows. At least two targets 14 are formed on the surface 10' of an Si substrate 10. The targets 14 are consisted of a striped thin layer of SiO2 15 having several-ten and several mum breadth strips being formed by selective plating consisting of a resin 17 and an exposed region 16 being surrounded with the region 17 to enlarge the contrast of strength of the reflected beam.
JP12496079A 1979-09-28 1979-09-28 Semiconductor wafer Pending JPS5649516A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12496079A JPS5649516A (en) 1979-09-28 1979-09-28 Semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12496079A JPS5649516A (en) 1979-09-28 1979-09-28 Semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS5649516A true JPS5649516A (en) 1981-05-06

Family

ID=14898473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12496079A Pending JPS5649516A (en) 1979-09-28 1979-09-28 Semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS5649516A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5528372A (en) * 1990-03-12 1996-06-18 Fujitsu Limited Alignment mark, laser trimmer and semiconductor device manufacturing process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5528372A (en) * 1990-03-12 1996-06-18 Fujitsu Limited Alignment mark, laser trimmer and semiconductor device manufacturing process

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