JPS564836A - Transfer and control system for display data - Google Patents

Transfer and control system for display data

Info

Publication number
JPS564836A
JPS564836A JP7878979A JP7878979A JPS564836A JP S564836 A JPS564836 A JP S564836A JP 7878979 A JP7878979 A JP 7878979A JP 7878979 A JP7878979 A JP 7878979A JP S564836 A JPS564836 A JP S564836A
Authority
JP
Japan
Prior art keywords
transfer
output
display data
disp
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7878979A
Other languages
Japanese (ja)
Other versions
JPS6212527B2 (en
Inventor
Toshifusa Iwamaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP7878979A priority Critical patent/JPS564836A/en
Publication of JPS564836A publication Critical patent/JPS564836A/en
Publication of JPS6212527B2 publication Critical patent/JPS6212527B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Calculators And Similar Devices (AREA)
  • Digital Computer Display Output (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

PURPOSE: To perform efficient data transfer by switching the rotation number of the driven timing signal, in operational processing and display data transfer.
CONSTITUTION: When the display data transfer instruction DISP output from the instruction decoder 10 is at 0, the gate of the AND circuit 18 of the timing signal generating circuit 12 is closed to output only the timing signals t1, t2, t3 and not to output t23. Further, the data read-out for the operating register is made in RAM3 at t1, data read-out for operated register is made at time t2, and the result of operation is written in operated register at t3. At the transfer of display data, DISP from the decoder 10 becomes 1 to output the signals t1, t2, t3, t23 from the circuit 12 and one cycle is sectioned into four. DISP is input to the AND circuits 28, 29 only while the delay circuit 31 is in operation, and the displayed data is sequentially output via the transfer gates 30, 30a in the timing of t32, t3, t1, t2.
COPYRIGHT: (C)1981,JPO&Japio
JP7878979A 1979-06-22 1979-06-22 Transfer and control system for display data Granted JPS564836A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7878979A JPS564836A (en) 1979-06-22 1979-06-22 Transfer and control system for display data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7878979A JPS564836A (en) 1979-06-22 1979-06-22 Transfer and control system for display data

Publications (2)

Publication Number Publication Date
JPS564836A true JPS564836A (en) 1981-01-19
JPS6212527B2 JPS6212527B2 (en) 1987-03-19

Family

ID=13671640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7878979A Granted JPS564836A (en) 1979-06-22 1979-06-22 Transfer and control system for display data

Country Status (1)

Country Link
JP (1) JPS564836A (en)

Also Published As

Publication number Publication date
JPS6212527B2 (en) 1987-03-19

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