JPS5645049A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5645049A
JPS5645049A JP12024779A JP12024779A JPS5645049A JP S5645049 A JPS5645049 A JP S5645049A JP 12024779 A JP12024779 A JP 12024779A JP 12024779 A JP12024779 A JP 12024779A JP S5645049 A JPS5645049 A JP S5645049A
Authority
JP
Japan
Prior art keywords
layer
gate electrode
mosi2
poly
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12024779A
Other languages
Japanese (ja)
Inventor
Toru Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP12024779A priority Critical patent/JPS5645049A/en
Publication of JPS5645049A publication Critical patent/JPS5645049A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To permit high operation of elements and to obtain superior stability and reliability multilayer wiring by forming the first layer wiring by a layer-built film of poly Si containing impurities and metallic silicide with high melting point wherein the second layer wiring is placed on the surface of the first layer wiring through an oxide film. CONSTITUTION:SiO2 2, doped poly Si 3 and MoSi2 4 are placed on a P type Si substrate 1 in piles and the first layer gate electrode is made by applying a resist mask and by electively etching the films 4, 3 in CF4 plasma. Furthermore, the film 2 is opened by the solution of HF group. Next, the films 2, 3, 4 are treated in oxidative atmosphere at a high temperature to cover with SiO2 5. MOSi2 6 is again formed and the second gate electrode 6 is made so that both side sections of the MOSi2 6 may partially lie on the first gate electrode. After that, two phase driving CCD having a two-layer transfer gate electrode is formed through predetermined processes. In this composition, limitation on manufacture is reduced and high speed operation of elements compared to the gate electrode consisting of a poly Si layer only will be possible. Furthermore, high stability and reliability multilayer wiring will be obtained.
JP12024779A 1979-09-19 1979-09-19 Manufacture of semiconductor device Pending JPS5645049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12024779A JPS5645049A (en) 1979-09-19 1979-09-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12024779A JPS5645049A (en) 1979-09-19 1979-09-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5645049A true JPS5645049A (en) 1981-04-24

Family

ID=14781469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12024779A Pending JPS5645049A (en) 1979-09-19 1979-09-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5645049A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154228A (en) * 1982-03-09 1983-09-13 Fujitsu Ltd Preparation of semiconductor device
JPS60140864A (en) * 1983-12-28 1985-07-25 Nec Corp Solid-state image pickup device
EP0406889A2 (en) * 1989-07-06 1991-01-09 Kabushiki Kaisha Toshiba Method of manufacturing a solid-state imaging device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5488783A (en) * 1977-12-26 1979-07-14 Cho Lsi Gijutsu Kenkyu Kumiai Semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5488783A (en) * 1977-12-26 1979-07-14 Cho Lsi Gijutsu Kenkyu Kumiai Semiconductor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154228A (en) * 1982-03-09 1983-09-13 Fujitsu Ltd Preparation of semiconductor device
JPS60140864A (en) * 1983-12-28 1985-07-25 Nec Corp Solid-state image pickup device
EP0406889A2 (en) * 1989-07-06 1991-01-09 Kabushiki Kaisha Toshiba Method of manufacturing a solid-state imaging device

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